• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 F
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• pp.2758-2760
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• 1999

ASIC chip design for motor control has been a subject of increasing interest since effective system-on-a-chip design methodology was developed. This paper investigates the design and implementation of ASIC chip for speed control of induction motor using VHDL which is a standarded hardware description language. The presented system is implemented using a simple electronic circuit based on FPGA.

• Applied Microscopy
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• 제50권
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• pp.22.1-22.6
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• 2020

In-situ transmission electron microscopy (TEM) holders that employ a chip-type specimen stage have been widely utilized in recent years. The specimen on the microelectromechanical system (MEMS)-based chip is commonly prepared by focused ion beam (FIB) milling and ex-situ lift-out (EXLO). However, the FIB-milled thin-foil specimens are inevitably contaminated with Ga⁺ ions. When these specimens are heated for real time observation, the Ga⁺ ions influence the reaction or aggregate in the protection layer. An effective method of removing the Ga residue by Ar⁺ ion milling within FIB system was explored in this study. However, the Ga residue remained in the thin-foil specimen that was extracted by EXLO from the trench after the conduct of Ar⁺ ion milling. To address this drawback, the thin-foil specimen was attached to an FIB lift-out grid, subjected to Ar⁺ ion milling, and subsequently transferred to an MEMS-based chip by EXLO. The removal of the Ga residue was confirmed by energy dispersive spectroscopy.

• 한국정밀공학회지
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• 제20권5호
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• pp.218-224
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• 2003

This paper describes a novel MEMS integration technique on a CMOS chip. MEMS integration on CMOS circuit has many advantages in view of manufacturing cost and reliability. The surface topography of a CMOS chip from a commercial foundry has 0.9 ${\mu}{\textrm}{m}$ bumps due to the conformal coating on aluminum interconnect patterns, which are used for addressing each MEMS element individually. Therefore, it is necessary to achieve a flat mirror-like CMOS chip fer the microelectromechanical system (MEMS) such as micro mirror array. Such CMOS chip needs an additional thickness of the dielectric passivation layer to ease the subsequent planarization process. To overcome a temperature limit from the aluminum thermal degradation, this study uses RF sputtering of silicon nitride at low temperature and then polishes the CMOS chip together with the surrounding dummy pieces to define a polishing plane. Planarization reduces 0.9 ${\mu}{\textrm}{m}$ of the bumps to less than 25 nm.

• 대한전자공학회논문지SD
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• 제47권1호
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• pp.86-93
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• 2010

반도체 공정 및 설계 기술의 발전에 따라 SoC에 보다 많은 기능이 포함되고 데이터 전송량 또한 급격히 증가하고 있다. 이에 따라 SoC 내부의 온 칩 네트워크에서 데이터 전송 속도가 전체 시스템의 성능에 큰 영향을 미치게 되어 이와 관련된 연구가 활발하게 진행되고 있다. 기존의 AHB를 대체하기 위한 온 칩 네트워크 프로토콜로 AXI와 OCP가 대표적으로 거론되고 있으나 전송 성능을 증가시키기 위해 신호선의 수가 크게 증가하여 인터페이스와 네트워크 하드웨어 설계가 매우 어렵고 기존에 널리 사용되던 AHB와 다른 프로토콜과의 호환성도 좋지 않다. 본 논문에서는 이를 개선하기 위한 새로운 온 칩 네트워크 프로토콜을 제안한다. 제안된 프로토콜은 신호선의 수를 기존의 AHB보다 줄이고 AXI 등 다른 프로토콜과의 호환성도 고려하였다. 성능 분석결과 AXI보다는 조금 떨어지는 성능을 보여주고 있으나 8-버스트 이상의 전송에서는 큰 차이가 없고 신호선 수대비 성능에서는 월등히 우수함을 확인하였다.

• 한국철도학회:학술대회논문집
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• 한국철도학회 2008년도 춘계학술대회 논문집
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• pp.572-578
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• 2008

As the railway transportation is getting faster and its operation speed has increased rapidly, its signal control has been complicated. For real time signal processing it is very important to prohibit any critical error from causing the system to malfunction. Therefore, handling complicated signals effectively while maintaining fault-tolerance capability is highly expected in modern railway transportation industry. In this paper, we suggest an SoC (Sytem-on-Chip) design method to integrate these complicated signal controlling mechanism with fault tolerant capability in a single chip. We propose an SoC solution which contains a high performance 32-bit embedded processor, digital filters and a PWM unit inside a single chip to implement ATO's, ATC's, ATP's and ATS's digital signal-processing units. We achieve an enhanced reliability against the calculation error by adding fault tolerance features to ensure the stability of each module.

• 한국정보통신학회논문지
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• 제15권3호
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• pp.632-638
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• 2011

본 논문은 고주파 시스템 온 칩 응용을 위한 온 칩 검사 대응 설계 (Design-for-Testability, DFT) 회로를 제안한다. 이러한 회로는 고주파 회로의 주요 성능 변수들 즉, 입력 임피던스, 전압이득, 잡음지수, 입력 전압 정재비 (VSWRin) 및 출력 신호대 잡음비 (SNRout)를 고가의 장비없이 측정 가능하다. 이러한 고주파 검사 회로는 DFT 칩으로부터 측정된 출력 DC 전압에 실제 고주파 소자의 성능을 제공하는 자체 개발한 이론적인 수학적 표현식을 이용한다. 제안한 DFT 회로는 외부 장비를 이용한 측정 결과와 비교해 볼 때 고주파 회로의 주요 성능 변수들에 대해 5.25GHz의 동작주파수에서 2%이하의 오차를 각각 보였다. DFT 회로는 고주파 소자 생산뿐만 아니라 시스템 검사 과정에서 칩들의 성능을 신속히 측정할 수 있으므로 불필요한 소자 복사를 위해 소요되는 엄청난 경비를 줄일 수 있으리라 기대한다.

• 한국공작기계학회논문집
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• 제18권1호
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• pp.116-121
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• 2009

Thermosonic flip chip bonding is an important technology for the electronic packaging due to its simplicity, cost effectiveness and clean and dry process. Mechanical properties of the horn and the shank, such as the natural frequency and the amplitude, have a great effect on the bonding capability of the transverse flip chip bonding system. In this research, two kinds of study are performed. The first is the new design of the clamp and the second is the effect of tolerance parameters to the performance of the system. The clamp with a bent shape is newly designed to hold the nodal point of the flip chip. The second is the effect of the design parameters on the vibration amplitude and planarity at the end of the shank. The variation of the tolerance parameters changes the amplitude and the frequency of the vibration of the shank. They, in turn, have an effect on the quantity of the plastic deformation of the gold ball bump, which determined the quality of the flip chip bonding. The tolerance parameters that give the great effect on the amplitude of the shank are determined using Taguchi's method. Error of set-up angle, the length and diameter of horn and error of the length of the shank are determined to be the parameters that have peat effect on the amplitude of the system.

• 한국생산제조학회지
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• 제20권5호
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• pp.559-563
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• 2011

Drop impact reliability assessment of solder joints on the flip chip is one of the critical issues for micro system packaging. Our previous researches have been showing that new solder ball compositions of Sn-3.0Ag-0.5Cu has better mechanical reliability than Sn-1.0Ag-0.5Cu. In this paper, dynamic reliability analysis using Finite Element Analysis (FEA) is carried out to assess the factors affecting flip chip in drop simulation. The design parameters are size and thickness of chip, and size, pitch and array of solder ball with composition of Sn1.0Ag0.5Cu. The board systems by JEDEC standard including 15 chips, solder balls and PCB are modeled with various design parameter combinations, and through these simulations, maximum yield stress and strain at each chip are shown at the solder balls. It is found that larger chip size, smaller chip array, smaller ball diameter, larger pitch, and larger chip thickness have bad effect on maximum yield stress and strain at solder ball of each chip.

• 유체기계공업학회:학술대회논문집
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• 유체기계공업학회 2006년 제4회 한국유체공학학술대회 논문집
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• pp.305-308
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• 2006

For controlling micro-flows inside a LOC (lab-on-a-chip) a syringe pump or an electronic device for EOF(electro-osmotic flow) have been used in general. However, these devices are so large and heavy that they are burdensome in the development of a portable micro-TAS (total analysis system). In this study, a new flow control system employing pressure chambers, digital switches and speed controllers was developed. This system could effectively control the micro-scale flows inside a LOC without any mechanical actuators or electronic devices We also checked the feasibility of this new control system by applying it to a LOC of micro-mixer type. Performance tests show that the developed control system has very good performance. Because the flow rate in LOC is controlled easily by throttling the speed controller, the flows in complicate microchannels network can be also controlled precisely.

• KIEE International Transactions on Electrophysics and Applications
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• 제4C권4호
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• pp.133-136
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• 2004

This research aims to develop a DNA chip array without an indicator. We fabricated a microelectrode array through photolithography technology. Several DNA probes were immobilized on an electrode. Then, target DNA was hybridized and measured electrochemically. Cyclic-voltammograms (CVs) showed a difference between the DNA probe and mismatched DNA in an anodic peak. This indicator-free DNA chip resulted in a sequence-specific detection of the target DNA.