• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.2
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• pp.176-181
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• 1988

In this paper, the LPC speech synthesizer with Multipulsse excitation is implemented using general-purpose DSP \ulcornerD7720. As the driving function for synthesis filter is used in the amplitude and position of pulse, the Voice/Unvoice decision and pitch period detectioncan be excluded. The synthesizer is implemented with DSP device which is operated on the interrupt mehtod with main computer and on the DMA mehtod with D/A converter. The comparision of synthetic and original waveform, alogn with the listening test, proves the validity of this system.

• Journal of IKEEE
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• v.3 no.1 s.4
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• pp.39-49
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• 1999

This paper describes a 1 GHz, low-phase-noise CMOS fractional-N frequency synthesizer with an integrated LC VCO. The proposed frequency synthesizer, which uses a high-order delta-sigma modulator to suppress the fractional spurious tones at all multiples of the fractional frequency resolution offset, has 64 programmable frequency channels with frequency resolution of $f_ref/64$. The measured phase noise is as low as -110 dBc/Hz at a 200 KHz offset frequency from a carrier frequency of 980 MHz. The reference sideband spurs are -73.5 dBc. The prototype is implemented in a $0.5{\mu}m$ CMOS process with triple metal layers. The active chip area is about $4mm^2$ and the prototype consumes 43 mW, including the VCO buffer power consumption, from a 3.3 V supply voltage.

• Journal of information and communication convergence engineering
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• v.3 no.3
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• pp.142-145
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• 2005

In this paper, a new programmable DLL (delay locked loop) based clock synthesizer is proposed. DLL has several inherent advantages, such as no phase accumulation error, fast locking and easy integration of the loop filter. This paper proposes a new programmable DLL that includes a PFD(phase frequency detector), a LSI(lock status indicator), and a VCDL(voltage controlled delay line) to generate multiple clocks. It can generate clocks from 3 to 9 times of input clock with $2{\mu}s$ locking time. The proposed DLL operating in the frequency range of 300MHZ-900MHz is verified by the HSPICE simulation with a $0.35{\mu}m$ CMOS process.

• Proceedings of the Korean Information Science Society Conference
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• 2002.04b
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• pp.349-351
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• 2002

XML문서를 작성하는데 있어서 그 규칙이나 DTD에 익숙하지 않은 개발자에게 구문 지향 편집기는 효율적인 환경을 제공해 준다. 이러한 구문 지향 편집기를 생성하는 도구로서 Synthesizer Generator등이 잘 알려져 있는데, 사용자는 Synthesizer Generator를 위해 구문 지향 편집기 생성 정보 표현 언어인 SSL(Syntheizer Specification Language)을 직접 작성해야 한다. 본 연구는 웹 문서 표준인 XML 구문 지향 편집기를 자동 생성하기 위한 방법을 제안한다. 제안된 방법은 입력된 XML DTD를 AST 형태로 변경하여DAG(Directed Acyclic Graph)를 추출하는 DAG 변환기, 생성된 DAG를 SSL로 변환하기 위한 DAG 핸들러와 SSL 변환기 모듈 그리고 변환된 SSL을 이용해 XML 구문 지향 편집기를 자동 생성하기 위한 Synthesizer Generator 사창을 포함한다. SSL 변환기는 SSL문서를 자동 생성하기 위한 모듈로서 추상 구문변환 모듈 역 파싱(Unparsing scheme)모듈 변형 규칙(Transformation rule) 표현 모듈로 구성된다. 사용자는 SSL변환기와 Synthesizer Generator의 사용을 통해 SSL을 직접 코딩해야 하는 노력과 불필요한 학습시간을 줄이고 빠르고 정확한 XML 구문 지향 편집기를 생성하므로 효율적인 XML 문서 작성할 수 있다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.2
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• pp.402-407
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• 2005

The PLL synthesizer is used in communication system until now because it have several merits, such as broad bandwidth, high accuracy and stability of frequency But it is difficult to use in the third generation mobile communication systems that need frequency hopping at a high speed because of its long frequency hopping time. In this paper, we designed the frequency synthesizer that generate frequencies randomly at a high speed using the DDS technology.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.4
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• pp.534-542
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• 2017

This paper presents a fast locking technique for a fractional-N PLL frequency synthesizer. The technique directly measures $K_{VCO}$ on a chip, computes the VCO's target tuning voltage for a given target frequency, and directly sets the loop filter voltage to the target voltage before the PLL begins the normal closed-loop locking process. The closed-loop lock time is significantly minimized because the initial frequency of the VCO are put very close to the desired final target value. The proposed technique is realized and designed for a 4.3-5.3 GHz fractional-N synthesizer in 65 nm CMOS and successfully verified through extensive simulations. The lock time is less than $12.8{\mu}s$ over the entire tuning range. Simulation verifications demonstrate that the proposed method is very effective in reducing the synthesizer lock time.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1986.10a
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• pp.28-34
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• 1986

The frequency synthesizer for Fast Frequency Hopping System musy be capable of a fast tuning with a small step frequency over wide band. The most conventional frequency synthesizer that uses the phase locked loop (PLL) enables the wide band problem but have a poor side of the low resolution and the transient response. In this paper, we have discussed the experimental results of a direct digital frequency synthesizer which can be applicable to the Fast Frequency Hopping System, using digital-to-analoq (D/A)conversion techniques. With this system we can find the merits of a fine resolution and the possibility of a fast tuning leaving the problems of transent frequency.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.208-211
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• 2000

This paper describes the design of a CMOS frequency synthesizer using programmable frequency divider with novel architecture. A novel architecture of programmable divider can be producted all of integer-N and fabricated by 0.65$\mu\textrm{m}$ 2-poly, 2-metal CMOS technology. Frequency synthesizer is simulated by 0.25$\mu\textrm{m}$ 2-poly, 5-metal CMOS technology. This circuit has settling time of 1.5${\mu}\textrm{s}$ and power consumption of 70㎽. Operating frequency of the frequency synthesizer is 820MHz∼l㎓ with a 2.5V supply voltage.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.3
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• pp.153-159
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• 2009

A CMOS frequency synthesizer for $5{\sim}6$ GHz UNII-band sub-harmonic direct-conversion receiver has been developed. For quadrature down-conversion with sub-harmonic mixing, octa-phase local oscillator (LO) signals are generated by an integer-N type phase-locked loop (PLL) frequency synthesizer. The complex timing issue of feedback divider of the PLL with large division ratio is solved by using multimodulus prescaler. Phase noise of the local oscillator signal is improved by employing the ring-type LC-tank oscillator and switching its tail current source. Implemented in a $0.18{\mu}m$ CMOS technology, the phase noise of the LO signal is lower than -80 dBc/Hz and -113 dBc/Hz at 100 kHz and 1MHz offset, respect-tively. The measured reference spur is lower than -70 dBc and the power consumption is 40 m W from a 1.8 V supply voltage.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.313-317
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• 2003

In this paper, ultra-wideband frequency synthesizer which operates at S-band ($2{\sim}4GHz$) is designed. Designed frequency synthesizer shows the frequency range of $2.2{\sim}4.0GHz$ and output power of $-2{\sim}3dBm$. Phase noise characteristics are measured below -92.0dBc/hz at 100kHz offset frequency in entire sweep range and lock time is measured below 3.55ms. Spurious level is below -62.33dBc at comparison frequency of 1MHz.