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Design of the Digital Frequency Synthesizer for High Speed Frequency Hopping by the DDS Method using CPLD  

Kim Girae (신라대학교 공과대학 전자공학과)
Choi Youngkyu (신라대학교 공과대학 전자공학과)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.9, no.2, 2005 , pp. 402-407 More about this Journal
Abstract
The PLL synthesizer is used in communication system until now because it have several merits, such as broad bandwidth, high accuracy and stability of frequency But it is difficult to use in the third generation mobile communication systems that need frequency hopping at a high speed because of its long frequency hopping time. In this paper, we designed the frequency synthesizer that generate frequencies randomly at a high speed using the DDS technology.
Keywords
CPLD; VHDL; DDS; PLL Synthesizer; Frequency Hopping;
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