Journal of information and communication convergence engineering

The Korea Institute of Information and Commucation Engineering (한국정보통신학회)
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A DLL Based Clock Synthesizer with Locking Status Indicator A DLL Based Clock Synthesizer with Locking Status Indicator

  • Ryu Young-Soo (Pukyong National University) ;
  • Choi Young-Shig (Dept. of Electronics and Telecommunication Engineering, Pukyong National University)
  • Published : 2005.11.01
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Abstract

In this paper, a new programmable DLL (delay locked loop) based clock synthesizer is proposed. DLL has several inherent advantages, such as no phase accumulation error, fast locking and easy integration of the loop filter. This paper proposes a new programmable DLL that includes a PFD(phase frequency detector), a LSI(lock status indicator), and a VCDL(voltage controlled delay line) to generate multiple clocks. It can generate clocks from 3 to 9 times of input clock with $2{\mu}s$ locking time. The proposed DLL operating in the frequency range of 300MHZ-900MHz is verified by the HSPICE simulation with a $0.35{\mu}m$ CMOS process.

Keywords

References

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