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http://dx.doi.org/10.5573/JSTS.2009.9.3.153

A CMOS Frequency Synthesizer for 5~6 GHz UNII-Band Sub-Harmonic Direct-Conversion Receiver  

Jeong, Chan-Young (Dept. EE., Hanyang University)
Yoo, Chang-Sik (Dept. EE., Hanyang University)
Publication Information
JSTS:Journal of Semiconductor Technology and Science / v.9, no.3, 2009 , pp. 153-159 More about this Journal
Abstract
A CMOS frequency synthesizer for $5{\sim}6$ GHz UNII-band sub-harmonic direct-conversion receiver has been developed. For quadrature down-conversion with sub-harmonic mixing, octa-phase local oscillator (LO) signals are generated by an integer-N type phase-locked loop (PLL) frequency synthesizer. The complex timing issue of feedback divider of the PLL with large division ratio is solved by using multimodulus prescaler. Phase noise of the local oscillator signal is improved by employing the ring-type LC-tank oscillator and switching its tail current source. Implemented in a $0.18{\mu}m$ CMOS technology, the phase noise of the LO signal is lower than -80 dBc/Hz and -113 dBc/Hz at 100 kHz and 1MHz offset, respect-tively. The measured reference spur is lower than -70 dBc and the power consumption is 40 m W from a 1.8 V supply voltage.
Keywords
Frequency synthesizer; integer-n type; voltage controlled oscillator (VCO); multi-modulus prescaler; phase noise; reference spur;
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