• JSTS:Journal of Semiconductor Technology and Science
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• 제9권2호
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• pp.110-116
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• 2009

The prominent advantages of Dual Material Surrounding Gate (DMSG) MOSFETs are higher speed, higher current drive, lower power consumption, enhanced short channel immunity and increased packing density, thus promising new opportunities for scaling and advanced design. In this Paper, we present Transconductance-to-drain current ratio and electric field distribution model for dual material surrounding gate (DMSGTs) MOSFETs. Transconductance-to-drain current ratio is a better criterion to access the performance of a device than the transconductance. This proposed model offers the basic designing guidance for dual material surrounding gate MOSFETs.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권1호
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• pp.92-97
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• 2008

In this Paper, we present a scaling theory for dual material surrounding gate (DMSGTs) MOSFETs, which gives a guidance for the device design and maintaining a precise subthreshold factor for given device parameters. By studying the subthreshold conducting phenomenon of DMSGTs, the effective conductive path effect (ECPE) is employed to acquire the natural length to guide the design. With ECPE, the minimum channel potential is used to monitor the subthreshold behavior. The effect of ECPE on scaling factor significantly improves the subthreshold swing compared to conventional scaling rule. This proposed model offers the basic designing guidance for dual material surrounding gate MOSFETs.

• Journal of Electrical Engineering and Technology
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• 제9권2호
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• pp.649-654
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• 2014

In this paper, an analytical model for Surrounding Gate (SG) metal-oxide- semiconductor field effect transistors (MOSFETs) considering quantum effects is presented. To achieve this goal, we have used variational approach for solving the Poission and Schrodinger equations. This model is developed to provide an analytical expression for inversion charge distribution function for all regions of device operation. This expression is used to calculate the other important parameters like inversion charge density, threshold voltage, drain current and gate capacitance. The calculated expressions for the above parameters are simple and accurate. This paper also focuses on the gate tunneling issue associated with high dielectric constant. The validity of this model was checked for the devices with different dimensions and bias voltages. The calculated results are compared with the simulation results and they show good agreement.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권3호
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• pp.221-226
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• 2008

A new two dimensional (2-D) analytical model for the Threshold Voltage on dual material surrounding gate (DMSG) MOSFETs is presented in this paper. The parabolic approximation technique is used to solve the 2-D Poisson equation with suitable boundary conditions. The simple and accurate analytical expression for the threshold voltage and sub-threshold swing is derived. It is seen that short channel effects (SCEs) in this structure is suppressed because of the perceivable step in the surface potential which screens the drain potential. We demonstrate that the proposed model exhibits significantly reduced SCEs, thus make it a more reliable device configuration for high speed wireless communication than the conventional single material surrounding gate (SMSG) MOSFETs.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권4호
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• pp.278-286
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• 2011

In this paper, we present a compact model of gate-voltage-dependent quantum effects in short-channel surrounding-gate (SG) metal-oxide-semiconductor field-effect transistors (MOSFETs). We based the model on a two-dimensional (2-D) analytical solution of Poisson's equation using cylindrical coordinates. We used the model to investigate the electrostatic potential and current sensitivities of various gate lengths ($L_g$) and radii (R). Schr$\ddot{o}$dinger's equation was solved analytically for a one-dimensional (1-D) quantum well to include quantum effects in the model. The model takes into account quantum effects in the inversion region of the SG MOSFET using a triangular well. We show that the new model is in excellent agreement with the device simulation results in all regions of operation.

• 한국전기전자재료학회논문지
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• 제31권5호
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• pp.278-282
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• 2018

We propose a SPICE model of drain-induced barrier lowering (DIBL) for a junctionless cylindrical surrounding gate (JLCSG) MOSFETs. To this end, the potential distribution in the channel is obtained via the Poisson equation, and the threshold voltage model is presented for the JLCSG MOSFET. In a JLCSG nano-structured MOSFET, a channel radius affects the carrier transfer as well as the channel length and oxide thickness; therefore, DIBL should be expressed as a function of channel length, channel radius, and oxide thickness. Consequently, it can be seen that DIBLs are proportional to the power of -3 for the channel length, 2 for the channel radius, 1 for the thickness of the oxide film, and the constant of proportionality is 18.5 when the SPICE parameter, the static feedback coefficient ${\eta}$, is between 0.2 and 1.0. In particular, as the channel radius and the oxide film thickness increase, the value of ${\eta}$ remains nearly constant.

• 전기전자학회논문지
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• 제23권1호
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• pp.29-34
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• 2019

본 논문에서는 10 nm 이하 무접합 원통형 MOSFET의 온-오프 전압 ${\Delta}V_{on-off}$에 대하여 고찰하였다. 문턱전압이하 전류가 $10^{-7}A$일 때 게이트 전압을 온 전압, $10^{-12}A$일 때 게이트 전압을 오프 전압으로 정의하고 그 차를 구하였다. 10 nm 이하에서는 터널링 전류를 무시할 수 없기 때문에 터널링 전류의 유무에 따라 ${\Delta}V_{on-off}$의 변화를 관찰하였다. 이를 위하여 포아송방정식을 이용하여 채널 내 전위분포를 구하였으며 WKB 근사를 이용하여 터널링 전류를 구하였다. 결과적으로 10 nm 이하 JLCSG MOSFET에서 터널링 전류에 기인하여 ${\Delta}V_{on-off}$가 증가하는 것을 알 수 있었다. 특히 8 nm 이하의 채널길이에서 급격히 증가하였으며 채널 반지름과 산화막 두께가 증가할수록 ${\Delta}V_{on-off}$는 증가하는 것을 알 수 있었다.