• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.119-122
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• 2008

In this paper, we describe the current status and issues of the oxide thin-film transistors (OTFTs), which attract much attention as an emerging new backplane technology replacing conventional silicon-based TFTs technologies. First, the unique benefits of OTFTs will be presented as a backplane for large-sized AMOLED including note-book PC, second TV and HD-TV. And then, the state-of-the-art transistor performance and uniformity characteristics of OTFTs will be highlighted. The obtained a-IGZO TFTs exhibited the field-effect mobility of $18\;cm^2/Vs$, threshold voltage of 1.8 V, on/off ratio of $10^9$, and subthreshold gate swing of 0.28 V/decade. In addition, the world largest-sized 12.1-inch WXGA active-matrix organic light emitting diode (AMOLED) display is demonstrated using indium-gallium-zinc oxide (IGZO) TFTs.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.439-442
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• 2006

We evaluated a-Si:H TFTs fabricated on polyimide substrate (PI) at the highest temperature of $160^{\circ}C$ with uniaxial and tensile strain to imitate flexible display. With tensile strain, the threshold voltage of a-Si:H TFTs have positive shift due to extra dangling bond formation in a-Si:H layer. However, no significant degradation of the subthreshold swing and effective mobility with tensile strain of a-Si:H TFTs indicates the similar level of band tail state. The metal wire with the width of $10\;{\mu}m$ for connection on flexible substrate can sustain with curvature radius 2.5 cm.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.136-136
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• 2011

반도체 및 전자기기 산업에 있어서 NVM은 아주 중요한 부분을 차지하고 있다. NVM은 디스플레이 분야에 많은 기여를 하고 있는데, 측히 AMOLED에 적용이 가능하여 온도에 따라 변하는 구동 전류, 휘도, color balance에 따른 문제를 해결하는데 큰 역할을 한다. 본 연구에서는 bottom gate 구조의 nc-Si NVM 실험을 진행하였다. P-type silicon substrate (0.01~0.02 ${\Omega}-cm$) 위에 Blocking layer 층인 SiO2 (SiH4:N2O=6:30)를 12.5nm증착하였고, Charge trap layer 층인 SiNx (SiH4:NH3=6:4)를 20 nm 증착하였다. 마지막으로 Tunneling layer 층인 SiOxNy은 N2O (2.5 sccm) 플라즈마 처리를 통해 2.5 nm 증착하였다. 이러한 ONO 구조층 위에 nc-Si을 50 nm 증착후에 Source와 Drain 층을 Al 120 nm로 evaporator 이용하여 증착하였다. 제작한 샘플을 전기적 특성인 Threshold voltage, Subthreshold swing, Field effect mobility, ON/OFF current ratio, Programming & Erasing 특성, Charge retention 특성 등을 알아보았다.

• Transactions on Electrical and Electronic Materials
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• v.16 no.4
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• pp.187-189
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• 2015

A charge-trap flash (CTF) thin film transistor (TFT) memory is proposed at a low-temperature process (≤ 450℃). The memory cell consists of a sputtered oxide-nitride-oxide (ONO) gate dielectric and Schottky barrier (SB) source/drain (S/D) junctions using nickel silicide. These components enable the ultra-low-temperature process to be successfully achieved with the ONO gate stacks that have a substrate temperature of room temperature and S/D junctions that have an annealing temperature of 200℃. The silicidation process was optimized by measuring the electrical characteristics of the Ni-silicided Schottky diodes. As a result, the Ion/Ioff current ratio is about 1.4×10⁵ and the subthreshold swing and field effect mobility are 0.42 V/dec and 14 cm²/V·s at a drain voltage of −1 V, respectively.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.8
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• pp.491-495
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• 2017

We investigated solution-processed indium-zinc oxide (IZO) thin-film transistors (TFTs) by inserting a 2-(4-biphenylyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole (PBD) buffer layer. This buffer layer efficiently tuned the energy level between the semiconducting oxide channel and metal electrode by increasing charge extraction, thereby enhancing the overall device performance: the IZO TFT with embedded PBD layer (thickness: 5 nm; width: $2,000{\mu}m$; length: $200{\mu}m$) exhibited a field-effect mobility of $1.31cm^2V^{-1}s^{-1}$, threshold voltage of 0.12 V, subthreshold swing of $0.87V\;decade^{-1}$, and on/off current ratio of $9.28{\times}10^5$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.11
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• pp.2709-2714
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• 2014

This paper has analyzed the change of threshold voltage and conduction path for the ratio of top and bottom gate oxide thickness of asymmetric double gate MOSFET. The asymmetric double gate MOSFET has the advantage that the factor to be able to control the current in the subthreshold region increases. The analytical potential distribution is derived from Poisson's equation to analyze the threshold voltage and conduction path for the ratio of top and bottom gate oxide thickness. The Gaussian distribution function is used as charge distribution. This analytical potential distribution is used to derive off-current and subthreshold swing. By observing the results of threshold voltage and conduction path with parameters of bottom gate voltage, channel length and thickness, projected range and standard projected deviation, the threshold voltage greatly changed for the ratio of top and bottom gate oxide thickness. The threshold voltage changed for the ratio of channel length and thickness, not the absolute values of those, and it increased when conduction path moved toward top gate. The threshold voltage and conduction path changed more greatly for projected range than standard projected deviation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.81-88
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• 2006

This paper describes a new linear operational transconductance amplifier (OTA). To improve the linearity of the OTA, we employ a mobility compensation circuit that combines the transistor paths operating at the triode and subthreshold regions. The common-mode control schemes consist of a common-mode feedback (CMFB) and common-mode feedforward (CMFF). The circuit enhances linearity of the transconductance (Gm) under the wide input voltage swing range. The proposed OTA shows ${\pm}1%$ Gm variation and the total harmonic distortion (THD) of below -73dB under the input voltage swing range of ${\pm}1.1V$. The OTA is implemented using a $0.35{\mu}m$ n-well CMOS process under 3.3V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.6
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• pp.1-7
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• 2004

We performed two-dimensional (20) computer-based modeling and simulation of FinFET by solving the coupled Poisson-Schrodinger equations quantum-mechanically in a self-consistent manner. The simulation results are carefully investigated for FinFET with gate length(Lg) varying from 10 to 80nm and with a Si-fin thickness($T_{fin}$) varying from 10 to 40nm. Current-voltage (I-V) characteristics are compared with the experimental data. Device optimization has been performed in order to suppress the short-channel effects (SCEs) including the sub-threshold swing, threshold voltage roll-off, drain induced barrier lowering (DIBL). The quantum-mechanical simulation is compared with the classical appmach in order to understand the influence of the electron confinement effect. Simulation results indicated that the FinFET is a promising structure to suppress the SCEs and the quantum-mechanical simulation is essential for applying nano-scale device structure.

• Journal of the Korean Ceramic Society
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• v.53 no.4
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• pp.411-416
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• 2016

Benzothienobenzothiophene ($C_8-BTBT$) is a soluble organic small molecule material with high crystallinity resulting from its strong self-organizing properties. In addition, the high mobility and easy fabrication of $C_8-BTBT$ make it very attractive in terms of organic thin-film transistors. In this work, we made $C_8-BTBT$ thin films by using the zone-casting method; we also used an organic solvent to treat the devices with solvent vapor annealing to improve the electrical properties. As a result, we confirmed improved mobility, threshold voltage, and subthreshold swing after solvent vapor annealing. To prove the effect of solvent vapor annealing, we used the simultaneous extraction model to extract the contact resistance from the current-voltage curve. We confirmed that the electrical properties improved with decreasing contact resistance.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.1
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• pp.50-54
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• 2018

In this study, a femtosecond laser pre-annealing technology based on indium zinc oxide (IZO) thin-film transistors (TFTs) was investigated. We demonstrated a stable pre-annealing process to analyze the change in the surface structures of thin-films, and we improved the electrical performance. Furthermore, static and dynamic electrical characteristics of IZO TFTs with n-channel inverters were observed. To investigate the static and dynamic responses of our solution-processed IZO TFTs, simple resistor-load-type inverters were fabricated by connecting a $1-M{\Omega}$ resistor. The femtosecond laser pre-annealing process based on IZO TFTs showed good performance: a field-effect mobility of $3.75cm_2/Vs$, an $I_{on}/I_{off}$ ratio of $1.8{\times}10^5$, a threshold voltage of 1.13 V, and a subthreshold swing of 1.21 V/dec. Our IZO-TFT-based N-MOS inverter performed well at operating voltage, and therefore, is a good candidate for advanced logic circuits and display backplane.