• Tribology and Lubricants
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• v.21 no.2
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• pp.71-76
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• 2005

This paper compares of mechanical tensile properties of 6 kinds of copper foil. The beam lead made with copper foil. Different from other package type such as plastic package, Chip Size Package has a reliability problem in beam lead rather than solder joint in board level. A new tensile loading system was developed using voice-coil actuator. The new tensile loading system has a load cell with maximum capacity of 20 N and a non-contact position measuring system based on the principle of capacitance micrometry with 0.1nm resolution for displacement measurement. Strain was calculated from the measured displacement using FE analysis. The comparison of mechanical properties helps designer of package to choose copper for ensuring reliability of beam lead in early stage of semiconductor development.

• Journal of Welding and Joining
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• v.29 no.1
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• pp.46-51
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• 2011

TSV technology raises several reliability concerns particularly caused by thermally induced stress. In traditional package, the thermo-mechanical failure mostly occurs as a result of the damage in the solder joint. In TSV technology, however, the driving failure may be TSV interconnects. In this study, the thermomechanical reliability of TSV technology is investigated using finite element method. Thermal stress and thermal fatigue phenomenon caused by repetitive temperature cycling are analyzed, and possible failure locations are discussed. In particular, the effects of via size, via pitch and bonding pad on thermo-mechanical reliability are investigated. The plastic strain generally increases with via size increases. Therefore, expected thermal fatigue life also increase as the via size decreases. However, the small via shows the higher von Mises stress. This means that smaller vias are not always safe despite their longer life expectancy. Therefore careful design consideration of via size and pitch is required for reliability improvement. Also the bonding pad design is important for enhancing the reliability of TSV structure.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.195-202
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• 2003

In this study, failure mechanisms of Au stud bumps/ACF flip chip joints were investigated underhigh current stressing condition. For the determination of allowable currents, I-V tests were performed on flip chip joints, and applied currents were measured as high as almost 4.2Amps $(4.42\times10^4\;Amp/cm^2)$. Degradation of flip chip joints was observed by in-situ monitoring of Au stud bumps-Al pads contact resistance. All failures, defined at infinite resistance, occurred at upward electron flow (from PCB pads to chip pads) applied bumps (UEB). However, failure did not occur at downward electron flow applied bumps (DEB). Only several $m\Omega$ contact resistance increased because of Au-Al intermetallic compound (IMC) growth. This polarity effect of Au stud bumps was different from that of solder bumps, and the mechanism was investigated by the calculation of chemical and electrical atomic flux. According to SEM and EDS results, major IMC phase was $Au_5Al_2$, and crack propagated along the interface between Au stud bump and IMC resulting in electrical failures at UEB. Therefore. failure mechanisms at Au stud bump/ACF flip chip Joint undo high current density condition are: 1) crack propagation, accompanied with Au-Al IMC growth. reduces contact area resulting in contact resistance increase; and 2) the polarity effect, depending on the direction of electrons. induces and accelerates the interfacial failure at UEBs.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.22 no.3_1spc
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• pp.504-508
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• 2013

This paper describes in detail the life prediction models and simulations of thermal fatigue under different mold compounds and chip sizes for wafer-level embedded SiP. Three-dimensional finite element models are built to simulate the viscoplastic behaviors for various mold compounds and chip sizes. In particular, the bonding parts between a mold and silicon nitride (Si3N4) are carefully modeled, and the strain distributions are studied. Three different chip sizes are used, and the effects of the mold compounds are observed. Through the numerical studies, it is found that type-C, which has a relatively lower Young's modulus and higher CTE, has a better fatigue life than the other mold compounds. In addition, the $4{\times}4$ chip has a shorter life than the $6{\times}6$ and $8{\times}8$ chips.

• Proceedings of the KWS Conference
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• 2005.11a
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• pp.225-227
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• 2005

Sn-8wt%Zn-3wt%Bi (이하, Sn-8Zn-3Bi) 솔더의 장기 신뢰성을 평가하기 위하여 열 충격 시험을 행하였다. 열 충격 시험은 $-40^{\circ}C$에서 $80^{\circ}C$범위에서 1000 사이클 동안 하였다. 접합 기판으로는 각각 OSP(Organic Solderability Preservative), Sn 그리고 Ni/Au 처리를 한 PCB(Printed Circuit Board) 패드를 사용하였다. 접합에 사용한 부품은 1608 Chip(Multi Layer Chip Capacitor, Chip Resistor) 으로 전극 부위에 Sn-37wt%Pb, Sn 도금하여 사용하였다. 솔더링 후 1608 Chip의 전단 강도와 솔더링부에서 미세조직 및 IMC(Inter Metallic Compound) 변화를 관찰하였다. 측정결과, Sn-8Zn-3Bi 솔더의 초기 전단 강도는 기판의 표면처리에 상관없이 약 40N 이상이었다. 그리고 열충격 시험 1000 사이클 후에는 모든 기판에서 2N 정도 약간의 강도 저하를 보였다.

• Journal of the Microelectronics and Packaging Society
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• v.7 no.4
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• pp.7-15
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• 2000

The purpose of this work is to evaluate the solderahility and characteristics of solder joints. Bridge defect of solder joint was examined in natural atmosphere and $N_2$ condition. Consequently, wettability was excellent for each of Sn-Pb plated Cu specimen, Sn plated Cu specimen, and Cu polished in $N_2$ condition. The wetting time in $N_2$ condition was shorter than that of natural atmosphere condition, showing the decreasing values of about 0.2~0.45 seconds. The max. wetting force under the $N_2$ condition was more increasing that of natural atmosphere condition, showing the increasing values of about 1.8~2.8 N. With the result of wetting balance test, the wetting time ($t_2$) and wetting farce according to increasing amount of $N_2$ from 10 1/min to 30 1/min, the wetting time ($t_2$) was reduced about 0.25 second and wetting force was increased about 2.3 N. In non-cleaning flux, when $N_2$ gas is applied, it is compensated to decrease of wettability. In the case of using the $N_2$ gas, the wettability was improved. The reason for improving wettability is due to preventing the formation of dross. The generation rate of bridge in $N_2$ condition decreased than that of natural atmosphere, and when the specimen had a fine pitch, the rate of bridge defects was considerably decreased in $N_2$ condition, showing the decreasing rate of 25~75%.

• Journal of the Microelectronics and Packaging Society
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• v.28 no.2
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• pp.65-70
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• 2021

In this study, interfacial properties and mechanical properties of joints were reported after Cu pads finished with organic solderability preservative (OSP) on flame retardant-4 (FR-4) printed circuit board (PCB) and electronic components were joined with a Sn-57Bi-1Ag solder paste by using a laser bonding process. The laser bonding process was performed under various bonding conditions with changing a laser power and a bonding time and effects of bonding conditions on interfacial and mechanical properties of joints were analyzed. In order to apply for industry, properties of bonding joints using a reflow bonding process which are widely used were compared. When the laser bonding process were performed, we observed that Cu₆Sn₅ intermetallic compounds (IMCs) were fully formed at the interface although the bonding times were very short about 2 and 3 s. Furthermore, void formations of the joints by using the laser bonding process were suppressed at the joints with comparing to the reflow bonding process and shear strengths of bonding joints were higher than that by using the reflow bonding process. Therefore, in spite of a very short bonding time, it is expected that joints will be stably formed and have a high mechanical strength by using the laser bonding process.

• Journal of the Microelectronics and Packaging Society
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• v.30 no.3
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• pp.40-50
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• 2023

Recently, the number of components of smartphones increases rapidly, while the PCB size continuously decreases. Therefore, 3D technology with a stacked PCB has been developed to improve component density in smartphone. For the s tacked PCB, it i s very important to obtain solder bonding quality between PCBs. We investigated the effects of the properties, thickness, and number of layers of interposer PCB and sub PCB on warpage of PCB through experimental and numerical analysis to improve the reliability of the stacked PCB. The warpage of the interposer PCB decreased as the thermal expansion coefficient (CTE) of the prepreg decreased, and decreased as the glass transition temperature (Tg) increased. However, if temperature is 240℃ or higher, the reduction of warpage is not large. As FR-5 was applied, the warpage decreased more compared to FR-4, and the higher the number and thickness of the prepreg, the lower the warpage. For sub PCB, the CTE was more important for warpage than Tg of the prepreg, and increase in prepreg thickness was more effective in reducing the warpage. The shear tests indicated that the dummy pad design increased bonding strength. The tumble tests indicated that crack occurrence rate was greatly reduced with the dummy pad.

• Journal of Energy Engineering
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• v.23 no.4
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• pp.88-94
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• 2014

In this paper, Thermal Shock tests were performed varying the composition of the solder and ribbon thickness (A-type:0.2mm/60Sn40Pb, B-type:0.25mm/60Sn40Pb, C-type:0.2 /62Sn36Ag2Pb, D-type:0.25mm/62Sn36Ag2Pb) for evaluating the long-term reliability about Ribbon junction of Silicon solar cells. Thermal Shock test condition was performed during the 600cycles having $-40^{\circ}C{\sim}85^{\circ}C$ temperature range each 15 minutes; One cycle time was 30min. As a result, the initial efficiency of the A-type, B-type, and C, D-type were showed 15.0%, 15.4% and 15.8% respectively. After thermal shock test, the efficiency decreasing-rate of each type were as follow that A-type was 13.8%, B-Type was 15.4%. C-Type and D-Type was 15.3% and 16.2%, respectively. Also, degradation of surface changes and I-V characteristic curves were showed that the series resistance of the A, C-type was increased. Also, current lowering starting point of C-type shown 0.05volt[v] earlier than that of A-type. And B, D-type shown characteristics of composite lowering efficiency such as increase of series resistance, decrease of parallel resistance and cell damage. Therefore Initial solderability and efficiency of specimens using the solder with SnAgPb were superior. But, It has inferior the long-term reliability. The test was confirmed that as the ribbon thickness increases, long-term reliability of solar cell will decrease.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.3
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• pp.35-40
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• 2008

Investigation on immersion gold layers was carried out using TEM analysis for the purpose of understanding the defect of immersion gold layer. The immersion gold layers prepared with three different types of baths were observed. The results showed that the defect structure of immersion gold layer is strongly dependent on the types of gold baths. Spherical defects of average 10 nm size were located along the grain boundaries for the specimen formed at KAu$(CN)_2$ bath containing no reducing agent. In the case of the specimen processed at KAu$(CN)_2$ bath containing a reducing agent, the spherical defects of 5-10 nm size were distributed randomly in grains as well as at grain boundaries. However, such defects disappeared almost completely when $Na_{3}Au(SO_3)_2$ bath was used to fabricate an immersion gold.