Journal of the Korean Society of Manufacturing Technology Engineers (한국생산제조학회지)

The Korean Society of Manufacturing Technology Engineers (한국생산제조학회)
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Thermal Fatigue Analysis of Wafer Level Embedded SiP by Changing Mold Compounds and Chip Sizes

몰드물성 종류 및 칩 크기 변화에 따른 웨이퍼 레벨 Sip에서의 열 피로 해석

  • Jang, Chong Min (Department of Mechanical System Design Engineering, Seoul National University of Science & Technology) ;
  • Kim, Seong Keol (Department of Mechanical System Design Engineering, Seoul National University of Science & Technology)
  • Received : 2013.03.29
  • Accepted : 2013.05.08
  • Published : 2013.06.15
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Abstract

This paper describes in detail the life prediction models and simulations of thermal fatigue under different mold compounds and chip sizes for wafer-level embedded SiP. Three-dimensional finite element models are built to simulate the viscoplastic behaviors for various mold compounds and chip sizes. In particular, the bonding parts between a mold and silicon nitride (Si3N4) are carefully modeled, and the strain distributions are studied. Three different chip sizes are used, and the effects of the mold compounds are observed. Through the numerical studies, it is found that type-C, which has a relatively lower Young's modulus and higher CTE, has a better fatigue life than the other mold compounds. In addition, the $4{\times}4$ chip has a shorter life than the $6{\times}6$ and $8{\times}8$ chips.

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References

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