• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2000년도 Proceedings of 5th International Joint Symposium on Microeletronics and Packaging
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• pp.43-55
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• 2000

In traditional electronic packages the die and the substrate are interconnected with fine wire. Wire bonding technology is limited to bond pads around the peripheral of the die. As the demand for I/O increases, there will be limitations with wire bonding technology. Flip chip technology eliminates the need for wire bonding by redistributing the bond pads over the entire surface of the die. Instead of wires, the die is attached to the substrate utilizing a direct solder connection. Although several steps and processes are eliminated when utilizing flip chip technology, there are several new problems that must be overcome. The main issue is the mismatch in the coefficient of thermal expansion (CTE) of the silicon die and the substrate. This mismatch will cause premature solder Joint failure. This issue can be compensated for by the use of an underfill material between the die and the substrate. Underfill helps to extend the working life of the device by providing environmental protection and structural integrity. Flux residues may interfere with the flow of underfill encapsulants causing gross solder voids and premature failure of the solder connection. Furthermore, flux residues may chemically react with the underfill polymer causing a change in its mechanical and thermal properties. As flip chip packages decrease in size, cleaning becomes more challenging. While package size continues to decrease, the total number of 1/0 continue to increase. As the I/O increases, the array density of the package increases and as the array density increases, the pitch decreases. If the pitch is decreasing, the standoff is also decreasing. This paper will present the keys to successful flip chip cleaning processes. Process parameters such as time, temperature, solvency, and impingement energy required for successful cleaning will be addressed. Flip chip packages will be cleaned and subjected to JEDEC level 3 testing, followed by accelerated stress testing. The devices will then be analyzed using acoustic microscopy and the results and conclusions reported.

• Journal of Welding and Joining
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• 제19권3호
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• pp.305-310
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• 2001

UBM-coated Si-wafer was fluxlessly soldered with glass substrate in $N_2$ atmosphere using plasma cleaning method. The bulk Sn-37wt.%Pb solder was rolled to the sheet of $100\mu\textrm{m}$ thickness in order to bond a solder disk by fluxless 1st reflow process. The oxide layer on the solder surface was analysed by AES(Auger Electron Spectroscopy). Through rolling, the oxide layer on the solder surface became thin, and it was possible to bond a solder disk on the Si-wafer with fluxless process in $N_2$ gas. The Si-wafer with a solder disk was plasma-cleaned in order to remove oxide layer formed during 1st reflow and soldered to glass by 2nd reflow process without flux in $N_2$ atmosphere. The thickness of oxide layer decreased with increasing plasma power and cleaning time. The optimum plasma cleaning condition for soldering was 500W 12min. The joint was sound and the thicknesses of intermetallic compounds were less than $1\mu\textrm{m}$.

• ETRI Journal
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• 제32권3호
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• pp.414-421
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• 2010

The interconnection mechanisms of a smart anisotropic conductive adhesive (ACA) during processing have been characterized. For an understanding of chemorheological mechanisms between the fluxing polymer and solder powder, a thermal analysis as well as solder wetting and coalescence experiments were conducted. The compatibility between the viscosity of the fluxing polymer and melting temperature of solder was characterized to optimize the processing cycle. A fluxing agent was also used to remove the oxide layer performed on the surface of the solder. Based on these chemorheological phenomena of the fluxing polymer and solder, an optimum polymer system and its processing cycle were designed for high performance and reliability in an electrical interconnection system. In the present research, a bonding mechanism of the smart ACA with a polymer spacer ball to control the gap between both substrates is newly proposed and investigated. The solder powder was used as a conductive material instead of polymer-based spherical conductive particles in a conventional anisotropic conductive film.

• 마이크로전자및패키징학회지
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• 제19권2호
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• pp.35-39
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• 2012

플립칩 접합시 발생하는 계면반응 거동과 접합특성을 계면에 생성되는 금속간화합물의 관점에서 접근하였다. 이를 위하여 Al/Cu와 Al/Ni의 under bump metallization(UBM) 층과 Sn-Cu계 솔더(Sn-3Cu, Sn-0.7Cu)와의 반응에 의한 금속간화합물의 형성거동 및 계면접합성을 분석하였다. Al/Cu UBM 상에서 Sn-0.7Cu 솔더를 리플로우한 경우에는 솔더/UBM 계면에서 금속간화합물이 형성되지 않았으며, Sn-3Cu를 리플로우한 경우에는 계면에서 생성된 $Cu_6Sn_5$ 금속간화합물이 spalling 되어 접합면이 분리되었다. 반면에 Al/Ni UBM 상에서 Sn-Cu계 솔더를 리플로우한 경우에는 0.7 wt% 및 3 wt%의 Cu 함량에 관계없이 $(Cu,Ni)_6Sn_5$ 금속간화합물이 계면에 형성되어 있었으며, 계면접합이 안정적으로 유지되었다.

• 대한기계학회논문집A
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• 제28권4호
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• pp.435-442
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• 2004

This paper presents a hermetic MEMS on-chip package bonded by a closed-loop AuSn solder-line. We design three different package specimens, including a substrate heated specimen without interconnection-line (SHX), a substrate heated specimen with interconnection-line (SHI) and a locally heated specimen with interconnection-line (LHI). Pressurized helium leak test has been carried out for hermetic seal evaluation in addition to the critical pressure test for bonding strength measurement. Substrate heating method (SHX, SHI) requires the bonding time of 40min. at 400min, while local heating method (LHI) requires 4 min. at the heating power of 6.76W. In the hermetic seal test. SHX, SHI and LHI show the leak rates of 5.4$\pm$6.7${\times}$$^{-10}$ mbar-l/s, 13.5$\pm$9.8${\times}$$^{-10}$ mbar-l/s and 18.5$\pm$9.9${\times}$$^{-10}$ mbar-l/s, respectively, for an identical package chamber volume of 6.89$\pm$0.2${\times}$$^{-10}$. In the critical pressure test, no fracture is found in the bonded specimens up to the applied pressure of 1$\pm$0.1MPa, resulting in the minimum bonding strength of 3.53$\pm$0.07MPa. We find that the present on-chip packaging using a closed AuSn solder-line shows strong potential for hermetic MEMS packaging with interconnection-line due to the hermetic seal performance and the shorter bonding time for mass production.

• ETRI Journal
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• 제35권6호
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• pp.1152-1155
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• 2013

A cost-effective and simple solder on pad (SoP) process is proposed for a fine-pitch microbump interconnection. A novel solder bump maker (SBM) material is applied to form a 60-${\mu}m$ pitch SoP. SBM, which is composed of ternary Sn3.0Ag0.5Cu (SAC305) solder powder and a polymer resin, is a paste material used to perform a fine-pitch SoP through a screen printing method. By optimizing the volumetric ratio of the resin, deoxidizing agent, and SAC305 solder powder, the oxide layers on the solder powder and Cu pads are successfully removed during the bumping process without additional treatment or equipment. Test vehicles with a daisy chain pattern are fabricated to develop the fine-pitch SoP process and evaluate the fine-pitch interconnection. The fabricated Si chip has 6,724 bumps with a 45-${\mu}m$ diameter and 60-${\mu}m$ pitch. The chip is flip chip bonded with a Si substrate using an underfill material with fluxing features. Using the fluxing underfill material is advantageous since it eliminates the flux cleaning process and capillary flow process of the underfill. The optimized bonding process is validated through an electrical characterization of the daisy chain pattern. This work is the first report on a successful operation of a fine-pitch SoP and microbump interconnection using a screen printing process.

• 마이크로전자및패키징학회지
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• 제25권2호
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• pp.1-8
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• 2018

In the soldering industry, a variety of lead-free solders have been developed as a part of restricting lead in electronic packaging. Sn-Ag-Cu (SAC) lead-free solder is regarded as one of the most superior candidates, owing to its low melting point and high solderability as well as the mechanical property. On the other hand, the mechanical property of SAC solder is directly influenced by intermetallic compounds (IMCs) in the solder joint. Although IMCs in SAC solder play an important role in bonding solder joints and impart strength to the surrounding solder matrix, a large amount of IMCs may cause poor strength, due to their brittle nature. In other words, the mechanical properties of SAC solder are of some concern because of the formation of large and brittle IMCs. As the IMCs grow, they may cause poor device performance, resulting in the failure of the electronic device. Therefore, new solder technologies which can control the IMC growth are necessary to address these issues satisfactorily. There are an advanced nanotechnology for microstructural refinement that lead to improve mechanical properties of solder alloys with nanoparticle additions, which are defined as nano-reinforced solders. These nano-reinforced solders increase the mechanical strength of the solder due to the dispersion hardening as well as solderability of the solder. This paper introduces the nano-reinforced solders, including its principles, types, and various properties.

• 반도체디스플레이기술학회지
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• 제10권2호
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• pp.103-108
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• 2011

Ultrasonic welding is widely used in bonding of the same kind or dissimilar materials. The important variable of ultrasonic bonding is the bonding pressure, bonding time and applied amplitude energy. These variables have to be optimized in order to obtain the optimum bonding results. In this research, the important factor to optimal bonding between metal and glass were experimentally investigated by applying design of experiment.

• 대한용접접합학회:학술대회논문집
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• 대한용접접합학회 2006년도 춘계 학술대회 개요집
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• pp.16-17
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• 2006

We researched by the characteristic of a anisotropic etching of Si wafer and the Si career concerning the flip chip solder bump. Connectors and Anisotropic Conductive Film (ACF) method was already applied to board-to-board interconnection. In place of them, we have focused on board to board interconnection with solder bump by Si carrier, which has been used as Flip chip bonding technology. A major advantage of this technology is that the Flexible Printed Circuit (FPC) is connected in the same solder reflow process with other surface mount devices. This technology can be applied to semiconductors and electronic devices for higher functionality, integration and reliability.

• 마이크로전자및패키징학회지
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• 제27권1호
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• pp.17-24
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• 2020

As an interconnect scaling faces a technical bottleneck, the device stacking technologies have been developed for miniaturization, low cost and high performance. To manufacture a stacked device structure, a vertical interconnect becomes a key process to enable signal and power integrities. Most bonding materials used in stacked structures are currently solder or Cu pillar with Sn cap, but copper is emerging as the most important bonding material due to fine-pitch patternability and high electrical performance. Copper bonding has advantages such as CMOS compatible process, high electrical and thermal conductivities, and excellent mechanical integrity, but it has major disadvantages of high bonding temperature, quick oxidation, and planarization requirement. There are many copper bonding processes such as dielectric bonding, copper direct bonding, copper-oxide hybrid bonding, copper-polymer hybrid bonding, etc.. As copper bonding evolves, copper-oxide hybrid bonding is considered as the most promising bonding process for vertically stacked device structure. This paper reviews current research trends of copper bonding focusing on the key process of Cu-SiO₂ hybrid bonding.