Journal of the Microelectronics and Packaging Society (마이크로전자및패키징학회지)

The Korean Microelectronics and Packaging Society (한국마이크로전자및패키징학회)
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Cu-SiO2 Hybrid Bonding

Cu-SiO2 하이브리드 본딩

  • Seo, Hankyeol (Department of Mechanical Engineering, Seoul National University of Science and Technology) ;
  • Park, Haesung (Graduate School of Nano-IT Design Convergence, Seoul National University of Science and Technology) ;
  • Kim, Sarah Eunkyung (Department of Mechanical Engineering, Seoul National University of Science and Technology)
  • 서한결 (서울과학기술대학교 나노IT디자인융합대학원) ;
  • 박해성 (서울과학기술대학교 일반대학원 기계공학과) ;
  • 김사라은경 (서울과학기술대학교 나노IT디자인융합대학원)
  • Received : 2020.01.20
  • Accepted : 2020.02.19
  • Published : 2020.03.30
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Abstract

As an interconnect scaling faces a technical bottleneck, the device stacking technologies have been developed for miniaturization, low cost and high performance. To manufacture a stacked device structure, a vertical interconnect becomes a key process to enable signal and power integrities. Most bonding materials used in stacked structures are currently solder or Cu pillar with Sn cap, but copper is emerging as the most important bonding material due to fine-pitch patternability and high electrical performance. Copper bonding has advantages such as CMOS compatible process, high electrical and thermal conductivities, and excellent mechanical integrity, but it has major disadvantages of high bonding temperature, quick oxidation, and planarization requirement. There are many copper bonding processes such as dielectric bonding, copper direct bonding, copper-oxide hybrid bonding, copper-polymer hybrid bonding, etc.. As copper bonding evolves, copper-oxide hybrid bonding is considered as the most promising bonding process for vertically stacked device structure. This paper reviews current research trends of copper bonding focusing on the key process of Cu-SiO2 hybrid bonding.

Keywords

References

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