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On-Chip Process and Characterization of the Hermetic MEMS Packaging Using a Closed AuSn Solder-Loop

사각고리형상의 AuSn 합금박막을 이용한 MEMS 밀봉 패키징 및 특성 시험

  • 서영호 (한국과학기술원 디지털나노구동연구단) ;
  • 김성아 (LG전자기술원 마이크로시스템 그룹) ;
  • 조영호 (한국과학기술원 디지털나노구동연구단) ;
  • 김근호 (LG전자기술원 마이크로시스템 그룹) ;
  • 부종욱 (LG전자기술원 마이크로시스템 그룹)
  • Published : 2004.04.01

Abstract

This paper presents a hermetic MEMS on-chip package bonded by a closed-loop AuSn solder-line. We design three different package specimens, including a substrate heated specimen without interconnection-line (SHX), a substrate heated specimen with interconnection-line (SHI) and a locally heated specimen with interconnection-line (LHI). Pressurized helium leak test has been carried out for hermetic seal evaluation in addition to the critical pressure test for bonding strength measurement. Substrate heating method (SHX, SHI) requires the bonding time of 40min. at 400min, while local heating method (LHI) requires 4 min. at the heating power of 6.76W. In the hermetic seal test. SHX, SHI and LHI show the leak rates of 5.4$\pm$6.7${\times}$$^{-10}$ mbar-l/s, 13.5$\pm$9.8${\times}$$^{-10}$ mbar-l/s and 18.5$\pm$9.9${\times}$$^{-10}$ mbar-l/s, respectively, for an identical package chamber volume of 6.89$\pm$0.2${\times}$$^{-10}$. In the critical pressure test, no fracture is found in the bonded specimens up to the applied pressure of 1$\pm$0.1MPa, resulting in the minimum bonding strength of 3.53$\pm$0.07MPa. We find that the present on-chip packaging using a closed AuSn solder-line shows strong potential for hermetic MEMS packaging with interconnection-line due to the hermetic seal performance and the shorter bonding time for mass production.

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