• Transactions of the Korean Society of Machine Tool Engineers
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• v.16 no.5
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• pp.134-139
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• 2007

This paper presents a computer-based analysis on the thermal shock characteristics of Pb-free solder joints and UBM in flip chip assemblies. Among four types of popular UBM systems, TiW/Cu system with 95.5Sn-3.9Ag-0.6Cu solder joints was chosen for simulation. A simple 3D finite element model was first created only including silicon die, mixture between underfill and solder joints, and substrate. The displacements due to CTE mismatch between silicon die and substrate was then obtained through FE analysis. Finally, the obtained displacements were applied as mechanical loads to the whole 2D FE model and the characteristics of flip chip assemblies were analyzed. In addition, based on the hyperbolic sine law, the accumulated creep strain of Pb-free solder joints was calculated to predict the fatigue life of flip chip assemblies under thermal shock environments. The proposed method for fatigue life prediction will be evaluated through the cross check of the test results in the future work.

• ETRI Journal
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• v.35 no.4
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• pp.625-631
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• 2013

For the formation of solder bumps with a fine pitch of 130 ${\mu}m$ on a printed circuit board substrate, low-volume solder on pad (LVSoP) technology using a maskless method is developed for SAC305 solder with a high melting temperature of $220^{\circ}C$. The solder bump maker (SBM) paste and its process are quantitatively optimized to obtain a uniform solder bump height, which is almost equal to the height of the solder resist. For an understanding of chemorheological phenomena of SBM paste, differential scanning calorimetry, viscosity measurement, and physical flowing of SBM paste are precisely characterized and observed during LVSoP processing. The average height of the solder bumps and their maximum and minimum values are 14.7 ${\mu}m$, 18.3 ${\mu}m$, and 12.0 ${\mu}m$, respectively. It is expected that maskless LVSoP technology can be effectively used for a fine-pitch interconnection of a Cu pillar in the semiconductor packaging field.

• Proceedings of the KWS Conference
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• 2006.05a
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• pp.227-229
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• 2006

3차원 실장을 하기 위해서 딥핑 방법으로 전기적 신호를 전달할 수 있는 비아를 가진 실리콘 웨이퍼를 제작하였다. 레이저를 이용하여 실리콘 웨이퍼에 개구부가 원형에 가까운 관통 홀을 형성하였다. 관통 홀의 벽에 도금 방법으로 시드 층을 형성하였다. 관통 홀의 충전 금속은 Sn-3.5Ag-0.7Cu 솔더를 사용하였다. 딥핑 방법으로 시드 층과 솔더 사이의 확산 현상 이용하여 전기적 신호를 전달 할 수 있는 비아를 형성하였다. 비아 내부에 일부 기공과 크랙이 발견되기도 했으나 딥핑 방법을 통해서 빠른 시간 내에 비아를 가진 실리콘 웨이퍼를 제작 할 수 있었다.

• Journal of the Microelectronics and Packaging Society
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• v.26 no.3
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• pp.43-49
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• 2019

In this study, a new approach using graphene oxide (GO) powder-composited Sn-3.0Ag-0.5Cu(in wt.%) solder paste for improving the bending reliability of solder joints between a flexible substrate and small outline package (SOP) was suggested. The GO addition slightly affected the melting temperature, however, the change in the melting temperature was not significant. Meanwhile, we observed the addition of GO could suppress IMC growth and IMC thickness of solder joint during the reflow process. Moreover, the cyclic bending test was also performed for evaluation of reliability in solder joint and we could improve the cyclic bending reliability of solder joint by adding GO powders. For 0.2 wt.% of GO added to the solder joint, the bending lifetime was increased to 20% greater than that without GO. Pull strength and ductility of the solder joint with GO were also higher than those of the joint without GO and it was assumed that this effect by adding GO could contribute to improve cyclic bending reliability of solder joint.

• ETRI Journal
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• v.35 no.2
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• pp.340-343
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• 2013

A novel bumping process using solder bump maker is developed for the maskless low-volume solder on pad (SoP) technology of fine-pitch flip chip bonding. The process includes two main steps: one is the aggregation of powdered solder on the metal pads on a substrate via an increase in temperature, and the other is the reflow of the deposited powder to form a low-volume SoP. Since the surface tension that exists when the solder is below its melting point is the major driving force of the solder deposit, only a small quantity of powdered solder adjacent to the pads can join the aggregation process to obtain a uniform, low-volume SoP array on the substrate, regardless of the pad configurations. Through this process, an SoP array on an organic substrate with a pitch of $130{\mu}m$ is successfully formed.

• Economic and Environmental Geology
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• v.42 no.3
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• pp.177-193
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• 2009

The Samgwang deposit consists of eight massive mesothermal quartz veins that filled NE and NW-striking fractures along fault zones in Precambrian granitic gneiss of the Gyeonggi massif. The mineralogy and paragenesis of the veins allow two separate discrete mineralization episodes(stage I=quartz and calcite stage, stage II-calcite stage) to be recognized, temporally separated by a major faulting event. The ore minerals are contained within quartz and calcite associated with fracturing and healing of veins that occurred during both mineralization episodes. The hydrothermal alteration of stage I is sericitization, chloritization, carbonitization, pyritization, silicification and argillization. Sericitic zone occurs near and at quartz vein and include mainly sericite, quartz, and minor illite, carbonates and chlorite. Chloritic zone occurs far from quartz vein and is composed of mainly chlorite, quartz and minor sericite, carbonates and epidote. Fe/(Fe+Mg) ratios of sericite and chlorite range 0.45 to 0.50(0.48$\pm$0.02) and 0.74 to 0.81(0.77$\pm$0.03), and belong to muscovite-petzite series and brunsvigite, respectiveIy. Calculated $Al_{IV}$-FE/(FE+Mg) diagrams of sericite and chlorite suggest that this can be a reliable indicator of alteration temperature in Au-Ag deposits. Calculated activities of chlorite end member are $a3(Fe_5Al_2Si_3O_{10}(OH)_6$=0.0275${\sim}$0.0413, $a2(Mg_5Al_2Si_3O_{10}(OH)_6$=1.18E-10${\sim}$7.79E-7, $a1(Mg_6Si_4O_{10}(OH)_6$=4.92E-10${\sim}$9.29E-7. It suggest that chlorite from the Samgwang deposit is iron-rich chlorite formed due to decreasing temperature from high temperature(T>450$^{\circ}C$). Calculated ${\alpha}Na^+$, ${\alpha}K^+$, ${\alpha}Ca^{2+}$, ${\alpha}Mg^{2+}$ and pH values during wallrock alteration are 0.0476($400^{\circ}C$), 0.0863($350^{\circ}C$), 0.0154($400^{\circ}C$), 0.0231($350^{\circ}C$), 2.42E-11($400^{\circ}C$), 7.07E-10($350^{\circ}C$), 1.59E-12($400^{\circ}C$), 1.77E-11($350^{\circ}C$), 5.4${\sim}$6.4($400^{\circ}C$), 5.3${\sim}$5.7($350^{\circ}C$)respectively. Gain elements(enrichment elements) during wallrock alteration are $TiO_2$, $Fe_2O_3(T)$,CaO, MnO, MgO, As, Ag, Cu, Zn, Ni, Co, W, V, Br, Cs, Rb, Sc, Bi, Nb, Sb, Se, Sn and Lu. Elements(Ag, As, Zn, Sc, Sb, Rb, S, $CO_2$) represents a potential tools for exploration in mesothermal and epithermal gold-silver deposits.

• Korean Journal of Metals and Materials
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• v.48 no.11
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• pp.1035-1040
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• 2010

The research efforts on GaN-based light-emitting diodes (LEDs) keep increasing due to their significant impact on the illumination industry. Surface mount technology (SMT) is widely used to mount the LED packages for practical application. In surface mount soldering both the device body and leads are intentionally heated by a reflow process. We studied on the effects of multiple reflows on microstructural variation and joint strength of the solder joints between the LED package and the substrate. In this study, Pb-free Sn-3.0Ag-0.5Cu solder and a finished pad with organic solderability preservatives (OSP) were employed. A $Cu_6Sn_5$ intermetallic compound (IMC) layer was formed during the multiple reflows, and the thickness of the IMC layerincreased with an increasing number of reflows. The shear force decreased after three reflows. From the observation of the fracture surface after a shear test, partially brittle fractures were observed after five reflows.

• Korean Journal of Metals and Materials
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• v.50 no.1
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• pp.71-77
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• 2012

We studied the effect of heat treatment on the microstructures and mechanical strength of the solder joints in the Light Emitting Diode (LED) packages. The commercial LED packages were mounted on the a flame resistance-4 (FR4) Printed Circuit Board (PCB) in the reflow process, and then the joints were aged at $125^{\circ}C$ for 100, 200, 300, 500 and 1000 hours, respectively. After the heat treatment, we measured the shear strength of the solder joints between the PCB and the LED packages to evaluate their mechanical property. We used Pb-free Sn-3.0Ag-0.5Cu solder to bond between the LED packages and the PCBs using two different surface finishes, Electroless Nickel-Immersion Gold (ENIG) and Electroless Nickel-Electroless Palladium-Immersion Gold (ENEPIG). The microstructure of the solder joints was observed by a scanning electron microscope (SEM). (Cu,Ni)6Sn5 intermetallic compounds (IMCs) formed between the solder and the PCB, and the thickness of the IMCs was increased with increasing aging time. The shear strength for the ENIG finished LED package increased until aging for 300 h and then decreased with increasing aging time. On the other hand, in the case of an ENEPIG finished LED package, the shear strength decreased after aging for 500 h.

• Korean Journal of Materials Research
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• v.19 no.6
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• pp.337-343
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• 2009

In this study, we optimized Pb-free Sn/Ni plating thickness and conditions were optimized to counteract the environmental regulations, such as RoHS and ELV(End-of Life Vehicles). The $B_{10}$ life verification method was also suggested to have been successful when used with the accelerated life test(ALT) for assessing Pb-free solder joint life of piezoelectric (PZT) ceramic resonator. In order to evaluate the solder joint life, a modified Norris-Landzberg equation and a Coffin-Manson equation were utilized. Test vehicles that were composed of 2520 PZT ceramic resonator on FR-4 PCB with Sn-3.0Ag-0.5Cu for ALT were manufactured as well. Thermal shock test was conducted with 1,500 cycles from $(-40{\pm}2)^{\circ}C$ to $(120{\pm}2)^{\circ}C$, and 30 minutes dwell time at each temperature, respectively. It was discovered that the thermal shock test is a very useful method in introducing the CTE mismatch caused by thermo-mechanical stress at the solder joints. The resonance frequency of test components was measured and observed the microsection views were also observed to confirm the crack generation of the solder joints.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.4
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• pp.1-9
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• 2011

Understanding the void characterization in the solder joints has become more important because of the application of lead free solder materials and its reliability in electronic packaging technology. According to the JEDEC 217 standard, it describes void types formed in the solder joints, and divides into some categories depending on the void position and formation cause. Based on the previous papers and the standards related to the void, reliability of the BGA solder joints is determined by the size of void, as well as the location of void inside the BGA solder ball. Prior to reflow soldering process, OSP(organic surface preservative) finished Cu electrode was exposed under $85^{\circ}C$/60%RH(relative humidity) for 168 h. Voids induced by the exposure of $85^{\circ}C$/60%RH became larger and bigger with increasing aging times. The void position has more influence on mechanical strength property than the amount of void growth does.