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http://dx.doi.org/10.4218/etrij.13.1912.0007

Optimization of Material and Process for Fine Pitch LVSoP Technology  

Eom, Yong-Sung (Components & Materials Research Laboratory, ETRI)
Son, Ji-Hye (Components & Materials Research Laboratory, ETRI)
Bae, Hyun-Cheol (Components & Materials Research Laboratory, ETRI)
Choi, Kwang-Seong (Components & Materials Research Laboratory, ETRI)
Choi, Heung-Soap (Department of Mechanical & Design Engineering, Hongik University Sejong)
Publication Information
ETRI Journal / v.35, no.4, 2013 , pp. 625-631 More about this Journal
Abstract
For the formation of solder bumps with a fine pitch of 130 ${\mu}m$ on a printed circuit board substrate, low-volume solder on pad (LVSoP) technology using a maskless method is developed for SAC305 solder with a high melting temperature of $220^{\circ}C$. The solder bump maker (SBM) paste and its process are quantitatively optimized to obtain a uniform solder bump height, which is almost equal to the height of the solder resist. For an understanding of chemorheological phenomena of SBM paste, differential scanning calorimetry, viscosity measurement, and physical flowing of SBM paste are precisely characterized and observed during LVSoP processing. The average height of the solder bumps and their maximum and minimum values are 14.7 ${\mu}m$, 18.3 ${\mu}m$, and 12.0 ${\mu}m$, respectively. It is expected that maskless LVSoP technology can be effectively used for a fine-pitch interconnection of a Cu pillar in the semiconductor packaging field.
Keywords
Maskless bumping; Sn/3.0Ag/0.5Cu; fine pitch; solder powder; resin; PCB;
Citations & Related Records
Times Cited By KSCI : 6  (Citation Analysis)
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1 K.-S. Choi et al., "Novel Bumping Material for Solder-on-Pad Technology," ETRI J., vol. 33, no. 4, Aug. 2011, pp. 637-640.   DOI   ScienceOn
2 S.C. Johnson, "Flip-Chip Packaging Becomes Competitive," Semiconductor Int., May 2009.
3 C.P. Wang, Materials for Advanced Packaging, Springer Science Business Media LLC, 2009.
4 K. Hikasa and H. Irie, "Advanced Solder Bumping Technology Through Super Solder," IEEE/CPMT Int Electron. Manufact. Technol. Symp., 1997, pp. 48-55.
5 M. Gerber et al., "Next Generation Fine Pitch Cu Pillar Technology - Enabling Next Generation Silicon Nodes," Proc. Electron. Compon. Technol. Conf., 2001, pp.612-618.
6 K.-S. Choi et al., "Novel Maskless Bumping for 3D Integration," ETRI J., vol. 32, no. 2, Apr. 2010, pp. 342-344.   DOI   ScienceOn
7 K.-J. Sung et al., "Novel Bumping and Underfill Technologies for 3D IC Integration," ETRI J., vol. 34, no. 5, Oct. 2012, pp. 706-712.   DOI   ScienceOn
8 K.-S. Choi et al., "Novel Bumping Process for Solder on Pad Technology," ETRI J., vol. 35, no. 2, Apr. 2013, pp. 340-343.   DOI   ScienceOn
9 R. Agarwal et al., "Cu/Sn Microbumps Interconnect for 3D TSV Chip Stacking" Proc. Electron. Compon. Technol. Conf., 2010, pp. 858-863.
10 Y.-S. Eom et al., "Characterization of Polymer Matrix and Low Melting Point Solder for Anisotropic Conductive Film," Microelectron. Eng., vol. 85, no. 2, Feb. 2008, pp. 327-331.   DOI   ScienceOn
11 K.-S. Jang et al., "Catalytic Behavior of Sn/Bi Metal Powder in Anhydride-Based Epoxy Curing," J. Nanosci. Nanotechnol., vol. 9, no. 12, 2009, pp. 7461-7466.
12 Y.-S. Eom et al., "Electrical Interconnection with a Smart ACA Composed of Fluxing Polymer and Solder Powder," ETRI J., vol. 32, no. 3, June 2010, pp. 414-420.   DOI   ScienceOn
13 Y.-S. Eom et al., "Characterization of a Hybrid Cu Paste as an Isotropic Conductive Adhesive," ETRI J., vol. 33, no. 6, Dec. 2011, pp. 864-870.   DOI
14 J.-W. Baek et al., "Chemo-Rheological Characteristic of a Self-Assembling Anisotropic Conductive Adhesive System Containing a Low-Melting Point Solder," Microelectron. Eng., vol. 87, no. 18, Oct. 2010, pp. 1968-1972.   DOI   ScienceOn