• Journal of KIISE:Computing Practices and Letters
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• v.16 no.7
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• pp.789-793
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• 2010

Recently, flash memory-based non-volatile cache (NVC) is emerging as an effective solution to enhance both I/O performance and energy consumption of storage systems. To get significant performance and energy gains by NVC, it would be better to use multi-level-cell (MLC) flash memories since it can provide a large capacity of NVC with low cost. However, the number of available program/erase cycles of MLC flash memory is smaller than that of single-level-cell (SLC) flash memory limiting the lifespan of NVC. To overcome such a limitation, SLC/MLC combined flash memory is a promising solution for NVC. In this paper, we propose an effective management scheme for heterogeneous SLC and MLC regions of the combined flash memory.

• Therapeutic Science for Rehabilitation
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• v.10 no.4
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• pp.39-52
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• 2021

Objective : This study aimed to identify the characteristics and analyze the quality of studies on memory improvement using a single-subject research design. Methods : Six studies were selected through the Research Information Sharing Service (RISS), Korean Studies Information Service System (KISS), and National Digital Science Library (NDSL). Keywords were memory training, stroke, early dementia, mild cognitive impairment, and single-subject research design. The characteristics and quality levels were analyzed between January 2011 and October 2020. Results : Regarding the quality level, the middle level (7-10 points) was 66.7% of the four articles, and the high level (11-14 points) was 33.3% of the two articles. Reversal designs were used in all studies. Independent variables were errorless learning, smartphone application, cognitive training system (CoTras), spaced retrieval training (SRT) with errorless learning, spaced retrieval training, and iPad applications. The dependent variables included memory, attention, electroencephalogram, instrumental activities of daily living, depression etc., which increased after the intervention. The total session, study period, and intervention time were varied. Conclusion : In single-subject research design related to memory training, occupational therapy intervention was confirmed as an effective method for improving memory and attention. The quality level of single-subject research design was moderate or higher, and high-quality level of studies should be conducted by additional design to increase the validity in the future.

• Journal of Ginseng Research
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• v.46 no.3
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• pp.435-443
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• 2022

Background: Post-traumatic stress disorder (PTSD) is a psychiatric disease that develops following exposure to a traumatic event and is a stress-associated mental disorder characterized by an imbalance of neuroinflammation. Korean Red Ginseng (KRG) is the herbal supplement that is known to be involved in a variety of pharmacological activities. We aimed to investigate the effects of KRG on neuroinflammation as a potential mechanism involved in single prolonged stress (SPS) that negatively influences memory formation and consolidation and leads to cognitive and spatial impairment by regulating BDNF signaling, synaptic proteins, and the activation of NF-κB. Methods: We analyzed the cognitive and spatial memory, and inflammatory cytokine levels during the SPS procedure. SPS model rats were injected intraperitoneally with 20, 50, or 100 mg/kg/day KRG for 14 days. Results: KRG administration significantly attenuated the cognitive and spatial memory deficits, as well as the inflammatory reaction in the hippocampus associated with activation of NF-κB in the hippocampus induced by SPS. Moreover, the effects of KRG were equivalent to those exerted by paroxetine. In addition, KRG improved the expression of BDNF mRNA and the synaptic protein PSD-95 in the hippocampus. Taken together, these findings demonstrate that KRG exerts memory-improving actions by regulating anti-inflammatory activities and the NF-κB and neurotrophic pathway. Conclusion: Our findings suggest that KRG is a potential functional ingredient for protecting against memory deficits in mental diseases, such as PTSD.

• Therapeutic Science for Rehabilitation
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• v.6 no.2
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• pp.71-83
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• 2017

Objective: This study was to develop and verify the effects of the exercise-cognitive combined dual-task training program on cognitive function and depression of the elderly with mild cognitive impairment(MCI). Methods: The subjects were randomly assigned to the exercise-cognitive combined dual-task training group(n=32) or single-task training group(n=31). To identify the effects on cognitive function, general cognitive function, frontal lobe function, and attention/working memory were measured. Depression was evaluated using Korean version of Geriatric Depression Scale. The outcome measurements were performed before and after the 8 weeks of intervention(2 days per week). Results: After 8 weeks, general cognitive function, frontal cognitive function, attention/working memory function, depression of the dual-task training group were significantly increased than those of the single-task training group(p<0.05). Conclusion: The results indicated that an exercise-cognitive combined dual-task training for MCI was effective in improving general cognitive function, frontal /executive function, attention/working memory function and reducing depression.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.72-85
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• 2007

The development of memory design and process technology enabled the production of high density memory. However, this increased the complexity of the memory making memory testing more complicated, and as a result, it brought about an increase in memory testing costs. Effective memory test algorithm must detect various types of defects within a short testing time, and especially in the case of port memory test algorithm, it must be able to detect single port memory defects, and all the defects in the dual port memory. The March A2PF algorithm proposed in this paper is an effective test algorithm that detects all types of defects relating to the duel port and single port memory through the short 18N test pattern.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.6
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• pp.742-750
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• 2018

In this paper, in order to enable zero-layer FTP cell using only 5V MOS devices on the basis of $0.13{\mu}m$ BCD process, the tunnel oxide thickness is used as the gate oxide thickness of $125{\AA}$ of the 5V MOS device at 82A. The HDNW layer, which is the default in the BCD process, is used. Thus, the proposed zero layer FTP cell does not require the addition of tunnel oxide and DNW mask. Also, from the viewpoint of memory IP design, a single memory structure which is used only for trimming analog circuit of PMIC chip is used instead of the dual memory structure dividing into designer memory area and user memory area. The start-up circuit of the BGR (Bandgap Reference Voltage) generator circuit is designed to operate in the voltage range of 1.8V to 5.5V. On the other hand, when the 64-bit FTP memory IP is powered on, the internal read signal is designed to maintain the initial read data at 00H. The layout size of the 64-bit FTP IP designed using the $0.13-{\mu}m$ Magnachip process .is $485.21{\mu}m{\times}440.665{\mu}m$($=0.214mm^2$).

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.5
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• pp.19-32
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• 1997

So far, the multiple path MINs to provide redundant paths in the traditional UPP MINs have been realized by adding additional hardware such as extra stages, duplicated data links, or multiple copies of sthe MIN. And the traditional MINs do not exploit locality: communication with all processor-memory paris takes the same amount of time. Also so far there has been little progress for exploiting locality of reference in MINs. In this paper, we present a new topology MIN, hybrid MIN that is constructed with 2N-3 SEs which is far fewer SEs than that of traditional MINs. Although the hybrid MIN is constructed with 2N-3 SEs, the hybrid MIN satisfies full access capability (FAC) and has redundant paths(but providing single path for 2 memory modules of each processor). Moreover the has redundant paths (but providing single path for 2 memory modules of each processor). Moreover the Hybrid MIN provides shortcut path between pairs which have frequent dat acommunication (locality of reference). Its performance under varing degrees of localized communication is analyzed.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.403-405
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• 2000

This paper describes a single transistor type ferroelectric field effect transistor (1Tr FeFET) memory cell scheme, which select one unit memory cell and program/read it. The well voltage can be controlled by isolating the common row well lines. Through applying bias voltage to Gate and Well, respectively, we implement If FeFET memory cell scheme in which interference problem is not generated and the selection of each memory cell is possible. The results of HSPICE simulations showed the successful operations of the proposed cell scheme.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.4
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• pp.514-523
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• 2017

In this paper, we propose Adaptive Writeback-aware Cache management (AWC) to prolong the lifetime of non-volatile main memory systems by reducing the number of writebacks. The last-level cache in AWC is partitioned into Least Recently Used (LRU) segment and LRU using Dirty block Precedence (DP-LRU) segment. The DP-LRU segment evicts clean blocks first for giving reuse opportunity to dirty blocks. AWC can also determine the efficient size of DP-LRU segment for reducing the number of writebacks according to memory access patterns of programs. In the performance evaluation, we showed that AWC reduced the number of writebacks up to 29% and 46%, and saved the energy of a main memory system up to 23% and 49% in a single-core and multi-core, respectively. AWC also reduced the runtime by 1.5% and 3.2% on average compared to previous cache managements for non-volatile main memory systems, in a single-core and a multi-core, respectively.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.42 no.6
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• pp.19-28
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• 2005

The multiprocessor architecture is a good method to improve the computer system performance. The CC-NUMA provides a single shared space with the physically distributed memories is used widely in the multiprocessor computer system. A CC-NUMA has the full-mapped directory for the shared memory md uses a remote cache memory for tile fast memory access. In this paper, we propose a processing node architecture for a CC-NUMA system and a cache coherency protocol on the physically distributed but logically shared system. We show an implementation result of the system which is adopted the cache coherency protocol.