그림 1. FTP cell (a) 회로도 (b) 공정단면도. Fig. 1. FTP cell: (a) circuit and (b) process cross-sectional view.
그림 2. 0.18㎛ BCD 공정으로 제작된 FTP 셀의 program voltage에 대한 program VT 와 erase VT 측정 결과. Fig. 2. Results of program VT and erase VT measurements with respect to program voltage for fabricated FTP cells based on the 0.18μm BCD process.
그림 3. 설계된 64비트 FTP 메모리 IP의 블록도. Fig. 3. Block diagram of the designed 64-bit FTP memory IP.
그림 4. BGR 회로도[9-10]. Fig. 4. BGR circuits: (a) concept circuit and (b) implemented circuit.
그림 5. Start-up 회로. Fig. 5 Start-up circuits: (a) conventional circuit and (b) proposed circuit.
그림 6. Sense amplifier 회로도 (a) OTP IP에 사용된 회로 (b) 제안된 회로. Fig. 6. Sense amplifier circuits: (a) circuit used in the OTP IP and (b) proposed circuit.
그림 7. 설계된 64비트 FTP IP의 레이아웃 사진. Fig. 7. Layout image of the designed 64-bit FTP IP.
그림 8. BGR 모의실험 결과 (a) 온도 변화에 대한 VREF 곡선 (b) VDD 변화에 대한 VREF 곡선 (c) power-up. Fig. 8. Simulatiob results of BGR: (a) VREF curve with respect to temperature, (b) VREF curve with respect to VDD, and (c) power-up.
그림 9. BL sense amplifier 회로에 대한 power-on reset 모의실험 결과. Fig. 9. Simulation result of power-on reset for BL sense amplifier.
표 1. MTP 셀의 특성 비교. Table 1. Characteristic comparison of MTP cells.
표 1. 64비트 FTP IP의 주요 특징. Table 2. Major specifications of 64-bit FTP IP.
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