Browse > Article

A Remote Cache Coherence Protocol for Single Shared Memory in Multiprocessor System  

Kim, Seong-Woon (Server Platform Research Team, ETRI)
Kim, Bo-Gwan (Dept. of Electronic Engineering, Chungnam University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea CI / v.42, no.6, 2005 , pp. 19-28 More about this Journal
Abstract
The multiprocessor architecture is a good method to improve the computer system performance. The CC-NUMA provides a single shared space with the physically distributed memories is used widely in the multiprocessor computer system. A CC-NUMA has the full-mapped directory for the shared memory md uses a remote cache memory for tile fast memory access. In this paper, we propose a processing node architecture for a CC-NUMA system and a cache coherency protocol on the physically distributed but logically shared system. We show an implementation result of the system which is adopted the cache coherency protocol.
Keywords
processor; cache; memory; CC-NUMA;
Citations & Related Records
연도 인용수 순위
  • Reference
1 SeongWoon Kim, Ando Ki, and Bogwan Kim, 'IA-32 Processor Interface Design for CC-NUMA system', In Proceedings Volume 3 of ITC-CSCC 2003, pages 1634-1637, July 9, 2003
2 Adi Golbert, Bob Farrell, Pete MacWilliams, Nabeel Sakran and Isic Silas, 'A Second Level Multiprocessing Cache for the i486DX and i860 Processors', Compcon Spring '92. Thirty-Seventh IEEE Computer Society International Conference, Digest of Papers., 24-28 Feb. 1992   DOI
3 James Archibald, 'High Performance Cache Coherence Protocols For Shared-Bus Multiprocessors', Technical Report, CS Department, University of Washington, Nov 17, 1987
4 Paul Sweazey and Alan Jay Smith, 'A class of compatible cache consistency protocols and their support by the IEEE Futurebus,' In Proceeding of the 13th Annual International Symposium on Computer Architecture', pages 412 - 423, 1986   DOI
5 SeongWoon Kim and SangSeok Shin, 'Modeling and Simulation of Memory Architecture on a Message Passing System', In Proceedings of the Joint Technical Conference 1996, pages 685-688, 1995
6 Hung-Chang Hsiao and Chung- Ta King, 'Performance Evaluation of Cache Depot on CC-NUMA Multiprocessors', Parallel and Distributed Systems, Proceedings International Conference, pp519 - 526,Dec. 1998   DOI
7 Lynn Choi, and Anddrew A. Chien, 'Integrating Network and Memory Hierachies in a Multicomputer Node Architecture', 8th International Parallel Processing Symposium, pp.10-17, April 26-29, 1994
8 David Culler, Jaswinder Pal Singh, and Annop Gupta, 'Parallel Computer Architecture : A Hardware/Software Approach',Morgan Kaufmann Publishers, 1997
9 SeongWoon Kim, Chulho Won, and SangMan Moh, 'The Main Processing Unit for the High-Speed Midrange Computer TICOM-III', In Proceedings of the Joint Technical Conference 1995, pages 455-458, 1995
10 Anant Agarwal, Richard Simoni, Mark Horowitz, and John Hennessy, 'An Evaluation of Directory Schemes for Cache Coherence', In Proceedings of the 15th Annual International Symposium on Computer Architecture, pp.280-289, 1988   DOI