• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.3
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• pp.479-485
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• 2006

The double gate(DG) MOSFET is a promising candidate to further extend the CMOS scaling and provide better control of short channel effect(SCE). DGMOSFETs, having ultra thin undoped Si channel for SCEs control, ale being validated for sub-20nm scaling. A novel analytical transport model for the subthreshold mode of DGMOSFETs is proposed in this paper. The model enables analysis of short channel effect such as the subthreshold swing(SS), the threshold voltage roil-off$({\Delta}V_{th})$ and the drain induced barrier lowering(DIBL). The proposed model includes the effects of thermionic emission and quantum tunneling of carriers through the source-drain barrier. An approximative solution of the 2D Poisson equation is used for the distribution of electric potential, and Wentzel-Kramers-Brillouin approximation is used for the tunneling probability. The new model is used to investigate the subthreshold characteristics of a double gate MOSFET having the gate length in the nanometer range $(5-20{\sim}nm)$ with ultra thin gate oxide and channel thickness. The model is verified by comparing the subthreshold swing and the threshold voltage roll-off with 2D numerical simulations. The proposed model is used to design contours for gate length, channel thickness, and gate oxide thickness.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.36 no.6
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• pp.424-429
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• 1987

It has been observed that the reduction rate of the inversion layer carrier mobility due to the increase of the longitudinal electric field(drain to source direction) decreases as the transverse electric field increases. The effects of this physicar phenomenon to the I-V characteristics of the short channel NMOSFET are studied. It is shown that these effects increase the drain Current in the saturatio region, which agrees with the genarally observed decrepancy between the experimental I-V charateristics and the I-V modeling which dose not include this physical phenomenon. Also it is shown that this effect becomes more important when the device channel length decreases and the device operates in the high electric field range.

• Journal of Digital Contents Society
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• v.7 no.3
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• pp.139-145
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• 2006

Short-range wireless transmission and networking technologies are becoming increasingly important in enabling useful mobile applications. Bluetooth and IEEE 802.11b standards are the most commonly deployed technologies for WPAN and WLAN. This paper investigates the effect of short range wireless channel on the performance of MC-CDMA/BPSK system and Bluetooth GFSK signal transmission in AWGN and Rician fading environments. And we investigate performance degradation due to interference effects in short range wireless channel. We firstly derive a equation for the bit error probability in additive white Gaussian noise depending on MC-CDMA/BPSK signal and GFSK modulation signal parameters according to the Bluetooth RF standard. Then, from this error rate expression we calculate the mean error probability for MC-CDMA/BPSK signal and Bluetooth GFSK signal in Rician fading and interference channel. In particular, the impacts of the Rician fading depth and interference level on the error probability is shown in BER performance figures.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.6
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• pp.428-435
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• 1998

SOI-like-bulk CMOS device is proposed, which having the advantages of SOI(Silicon On Insulator) and protects short channel effects efficiently with adding partial epitaxial process at standard CMOS process. SOI-like-bulk NMOS and PMOS with 0.25${\mu}{\textrm}{m}$ gate length have designed and optimized through analyzing the characteristics of these devices and applying again to the design of processes. The threshold voltages of the designed NMOS and PMOS are 0.3[V], -0.35[V] respectively and those have shown the stable characteristics under 1.5[V] gate and drain voltages. The leakage current of typical bulk-CMOS increase with shortening the channel length, but the proposed structures on this a study reduce the leakage current and improve the subthreshold characteristics at the same time. In addition, subthreshold swing value, S is 70.91[mV/decade] in SOI-like-bulk NMOS and 63.37[mV/ decade] SOI-like-bulk PMOS. And the characteristics of SOI-like-bulk CMOS are better than those of standard bulk CMOS. To validate the circuit application, CMOS inverter circuit has designed and transient & DC transfer characteristics are analyzed with mixed mode simulation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.10
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• pp.2267-2272
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• 2012

This study has presented the analysis of subthreshold swings based on scaling theory for double gate MOSFET. To solve the analytical potential distribution of Poisson's equation, we use Gaussian function to charge distribution. The scaling theory has been used to analyze short channel effect such as subthreshold swing degradation. These scaling factors for gate length, oxide thickness and channel thickness has been modified with the general scaling theory to include effects of double gates. We know subthreshold swing degradation is rapidly reduced when scaling factor of gate length is half of general scaling factor, and parameters such as projected range and standard projected deviation have greatly influenced on subthreshold swings.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.3
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• pp.189-196
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• 1989

In this paper, BICMOS gate array technology that has CMOS devices for logic applications and bipolar devices for driver applications is presented. An optimized poly gate p-well CMOS process is chosen to fabricate the BICMOS gate array system and the basic concepts to design these devices are to improve the characteristics of bipolar & CMOS device with simple process technology. As the results hFE value is 120(Ic=1mA) for transistor, and there is no short channel effects for CMOS devices which have Leff to 1.25um and 1.35um for n-channel, respectively, 0.8nx gate delay time of 41 stage ring oscillators is obtained.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.4
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• pp.793-798
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• 2012

In this paper, dependence of subthreshold current has been analyzed for doping distribution and channel structure of double gate(DG) MOSFET. The charge distribution of Gaussian function validated in previous researches has been used to obtain potential distribution in Poisson equation. Since DGMOSFETs have reduced short channel effects with improvement of current controllability by gate voltages, subthreshold characteristics have been enhanced. The control of current in subthreshold region is very important factor related with power consumption for ultra large scaled integration. The deviation of threshold voltage has been qualitatively analyzed using the changes of subthreshold current for gate voltages. Subthreshold current has been influenced by doping distribution and channel dimension. In this study, the influence of channel length and thickness on current has been analyzed according to intensity and distribution of doping.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.3
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• pp.672-677
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• 2013

This paper have analyzed the change of breakdown voltage for channel dimension of double gate(DG) MOSFET. The breakdown voltage to have the small value among the short channel effects of DGMOSFET to be next-generation devices have to be precisely analyzed. The analytical solution of Poisson's equation have been used to analyze the breakdown voltage, and Gaussian function been used as carrier distribution to analyze closely for experimental results. The breakdown voltages have been analyzed for device parameters such as channel thickness and doping concentration, and projected range and standard projected deviation of Gaussian function. Since this potential model has been verified in the previous papers, we have used this model to analyze the breakdown voltage. As a result, we know the breakdown voltage is influenced on Gaussian function and device parameters for DGMOSFET.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.811-814
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• 2012

This paper have analyzed the change of breakdown voltage for channel dimension of double gate(DG) MOSFET. The breakdown voltage to have the small value among the short channel effects of DGMOSFET to be next-generation devices have to be precisely analyzed. The analytical solution of Poisson's equation have been used to analyze the breakdown voltage, and Gaussian function been used as carrier distribution to analyze closely for experimental results. The breakdown voltages have been analyzed for device parameters such as channel thickness and doping concentration, and projected range and standard projected deviation of Gaussian function. Since this potential model has been verified in the previous papers, we have used this model to analyze the breakdown voltage. Resultly, we know the breakdown voltage is influenced on Gaussian function and device parameters for DGMOSFET.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.887-890
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• 2005

The double gate(DG) MOSFET is a promising candidate to further extend the CMOS scaling and provide better control of short channel effect(SCE). DGMOSFETs, having ultra thin updoped Si channel for SCEs control, are being validated for sub-20nm scaling, A channel effects such as the subthreshold swing(SS), and the threshold voltage roll-off(${\Delta}V_{th}$). The propsed model includes the effects of thermionic emission and quantum tunneling of carriers through the source-drain barrier. The proposed model is used to design contours for gate length, channel thickness, and gate oxide thickness.