• 대한전자공학회논문지SD
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• 제41권3호
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• pp.15-30
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• 2004

본 연구는 게이트 매몰형 단채널 GaAs MESFET의 암전류 특성과 광전류 특성을 해석적으로 모델링하였다. 모델링 결과, 광조사에 의한 중성영역내의 광 전도도의 증가 보다 공핍층 내의 광 기전력 발생에 따른 공핍층 폭의 감소효과로 인한 드레인 전류의 증가가 크게 일어남을 보이고 있다. 중성영역의 케리어 밀도 변화는 1차원 케리어 연속 방정식으로부터 도출하였으며, 광 기전력 도출은 게이트-공핍층 경계면의 광전류와 열전자 방출전류가 상쇄되는 조건으로 도출하였다. 드레인전압 인가에 따른 단채널 소자의 채널 방향의 전계효과를 고려한 2차원 Poisson 방정식의 해법을 제안하였다. 모델링 결과를 시뮬레이션한 결과, 적절한 암전류 및 광전류 특성에 대한 통합적 모델이 얻어짐을 확인하였다.

• 한국전기전자재료학회논문지
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• 제31권2호
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• pp.74-79
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• 2018

In this report, the results of a systematic study on the effects of polycrystalline silicon gate depletion on the reliability characteristics of metal-oxide semiconductor field-effect transistor (MOSFET) devices were discussed. The devices were fabricated using standard complimentary metal-oxide semiconductor (CMOS) processes, wherein phosphorus ion implantation with implant doses varying from $10^{13}$ to $5{\times}10^{15}cm^{-2}$ was performed to dope the polycrystalline silicon gate layer. For implant doses of $10^{14}/cm^2$ or less, the threshold voltage was increased with the formation of a depletion layer in the polycrystalline silicon gate layer. The gate-depletion effect was more pronounced for shorter channel lengths, like the narrow-width effect, which indicated that the gate-depletion effect could be used to solve the short-channel effect. In addition, the hot-carrier effects were significantly reduced for implant doses of $10^{14}/cm^2$ or less, which was attributed to the decreased gate current under the gate-depletion effects.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권6호
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• pp.847-853
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• 2016

Applications of Si have been increasingly exploited and extended to More-Moore, More-than-Moore, and beyond-CMOS approaches. Ge is regarded as one of the supplements for Si owing to its higher carrier mobilities and peculiar band structure, facilitating both advanced and optical applications. As an emerging metal-oxide device, the junctionless field-effect transistor (JLFET) has drawn considerable attention because of its simple process, less performance fluctuation, and stronger immunity against short-channel effects due to the absence of anisotype junctions. In this study, we investigated lateral field scalability, which is equivalent to channel-length scaling, in Si and Ge JLFETs. Through this, we can determine the usability of Si CMOS and hypothesize its replacement by Ge. For simulations with high accuracy, we performed rigorous modeling for ${\mu}_n$ and ${\mu}_p$ of Ge, which has seldom been reported. Although Ge has much higher ${\mu}_n$ and ${\mu}_p$ than Si, its saturation velocity ($v_{sat}$) is a more determining factor for maximum $I_{on}$. Thus, there is still room for pushing More-Moore technology because Si and Ge have a slight difference in $v_{sat}$. We compared both p- and n-type JLFETs in terms of $I_{on}$, $I_{off}$, $I_{on}/I_{off}$, and swing with the same channel doping and channel length/thickness. $I_{on}/I_{off}$ is inherently low for Ge but is invariant with $V_{DS}$. It is estimated that More-Moore approach can be further driven if Si is mounted on a JLFET until Ge has a strong possibility to replace Si for both p- and n-type devices for ultra-low-power applications.

• 상하수도학회지
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• 제22권1호
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• pp.113-120
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• 2008

A large majority of clearwell must be modified with maintaining the present baffles since they were underground built with the material like concrete. Therefore it is unreasonable to apply the previous research in clearwell modification which is studied with the assumption that distance between baffles is constant. In this study, internal short-circuiting estimation method (ISEM), which has the advantage of being applied at any condition, is applied to evaluate modification of A clearwell and modify B and C clerwell which have unusual characteristics. After analyzing the hydraulic efficiency at current state, modifications, where baffles, intra basins and diffuser walls are additionally installed, are considered and evaluate using ISEM. And the effect of intra basin and diffuser wall on $T_{10}/T$ is estimated and application feasibility of ISEM is evaluated. The improvement of intra basins is almost same with that of baffles. Also, short-circuiting in effluent zone can be reduced with the same level of channel zone if intra basin is added in effluent zone. However, effect range is restricted to the next channel zone. Diffuser wall can obtain the lower ISI than minimum ISI of cases where baffles and intra basins are installed. Therefore, additional improvement of $T_{10}/T$ value can be expected after $T_{10}/T$ value converges maximum only using baffles

• Journal of Electrical Engineering and Technology
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• 제12권6호
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• pp.2324-2332
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• 2017

This paper presents the electrical performances of novel AlGaSb/InGaAs heterojunction-based vertical-tunneling field-effect transistor (VTFET). The device performance was investigated in views of the on-state current ($I_{on}$), drain-induced barrier thinning (DIBT), and subthreshold swing (SS) as the gate length ($L_G$) was scaled down. The proposed TFET with a $L_G$ of 5 nm operated with an $I_{on}$ of $1.3mA/{\mu}m$, a DIBT of 40 mV/V, and an SS of 23 mV/dec at a drain voltage ($V_{DS}$) of 0.23 V. The proposed TFET provided approximately 25 times lower DIBT and 12 times smaller SS compared with the conventional $L_G$ of 5 nm TFET. The AlGaSb/InGaAs VTFET showed extremely high scalability and strong immunity against short-channel effects.

• 대한전자공학회논문지SD
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• 제45권10호
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• pp.15-22
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• 2008

기존의 MOSFET는 단채널 현상의 증가로 인하여 스케일링에 한계를 가지고 있다. Double-Gate MOSFET (DG-MOSFET)는 소자의 길이가 축소되면서 나타나는 단채널 현상을 효과적으로 제어하는 차세대 소자이다. DG-MOSFET으로 소자를 축소시키면 채널 길이가 10nm 이하에서 게이트 방향뿐만 아니라 소스와 드레인 방향에서도 양자 효과가 발생한다. 또한 게이트 길이가 매우 짧아지면 ballistic transport 현상이 발생한다. 따라서 본 연구에서는 2차원 양자 효과와 ballistic transport를 고려하여 DG-MOSFET의 특성을 분석하였다. 또한 단채널 효과를 줄이기 위해서 $t_{si}$와 underlap 그리고 lateral doping gradient를 이용하여 소자 구조를 최적화하였다.

• 한국전기전자재료학회논문지
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• 제31권3호
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• pp.146-151
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• 2018

In this study, we compared the threshold-voltage extraction methods of accumulation-type JLDG (junctionless double-gate) MOSFETs (metal-oxide semiconductor field-effect transistors). Threshold voltage is the most basic element of transistor design; therefore, accurate threshold-voltage extraction is the most important factor in integrated-circuit design. For this purpose, analytical potential distributions were obtained and diffusion-drift current equations for these potential distributions were used. There are the ${\phi}_{min}$ method, based on the physical concept; the linear extrapolation method; and the second and third derivative method from the $I_d-V_g$ relation. We observed that the threshold-voltages extracted using the maximum value of TD (third derivatives) and the ${\phi}_{min}$ method were the most reasonable in JLDG MOSFETs. In the case of 20 nm channel length or more, similar results were obtained for other methods, except for the linear extrapolation method. However, when the channel length is below 20 nm, only the ${\phi}_{min}$ method and the TD method reflected the short-channel effect.

• The Journal of the Acoustical Society of Korea
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• 제27권3E호
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• pp.69-76
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• 2008

Measurements of bubble size and distribution in the surface layer of the sea, wind speed, and variation of ocean environments were made continually over a four-day period in an experiment conducted in the South Sea of Korea during 17-20 September 2007. Theoretical background of bubble population model indicates that bubble population is a function of the depth, range and wind speed and bubble effects on sound speed shows that sound speed varies with frequency. Observational evidence exhibited that the middle size bubble population fit the model very well, however, smaller ones can not follow the model probably due to their short lifetime. Meanwhile, there is also a hysteresis effect of void fraction. Observational evidence also indicates that strong changes in sound speed are produced by the presence of swarms of micro bubbles especially from 7 kHz to 50 kHz, and calculation results are consistent with the measured data in the high frequency band, but inconsistent in the low frequency band. Based on the measurements of the sound speed and high frequency transmission configuration in the bubble layer, we present an estimation of underwater acoustic channel capacity in the bubble layer.

• 대한전자공학회논문지SD
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• 제47권2호
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• pp.1-6
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• 2010

수직형 채널을 가지는 4-비트 SONOS 플래시 메모리를 이용하여, 고집적화된 3차원 형태의 NOR 플래시 메모리 어레이를 제안하였다. 수직형 채널을 가지기 때문에, 집적도의 제한 없이 충분히 긴 채널을 가질 수 있다. 이로 인하여, 짧은 채널의 멀티 비트 메모리에서 발생할 수 있는 비트 간의 간섭효과, 짧은 채널 효과, 및 전하 재분포 현상을 해결 할 수 있다. 또한, 제시된 어레이는 3차원 형태를 기반으로 고집적화되어, 발표된 NOR 중에서 최소의 셀 크기 값인 $1.5F^2$/bit을 가진다.

• 한국정보통신학회논문지
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• 제15권8호
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• pp.1764-1770
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• 2011

본 연구에서는 이중게이트 MOSFET의 채널내 도핑분포에 따른 문턱전압이하 스윙을 분석하였다. DGMOSFET는 차세대 나노소자로서 단채널효과를 감소시킬 수 있다는 장점 때문에 많은 연구가 진행 중에 있다. 문턱전압이하 스윙특성의 저하는 중요한 단채널 효과로서 디지털소자응용에서 매우 심각한 영향을 미치고 있다. 이러한 문턱 전압이하 스윙특성의 저하를 이중게이트(Double Gate; DG) MOSFET의 구조적 파라미터 및 채널 내 도핑분포함수의 변화에 따라 분석하고자 한다. 이를 위하여 가우시안 분포함수를 이용하여 포아송방정식의 해석학적 모델을 유도하였다. 본 논문에서 사용한 해석학적 포아송방정식의 전위분포모델 및 문턱전압이하 스윙모델의 타당성을 입증하기 위하여 수치해석학적 결과값과 비교하였으며 이 모델을 이용하여 이중게이트 MOSFET의 문턱전압이하 스윙을 분석하였다.