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Highly Integrated 3-dimensional NOR Flash Array with Vertical 4-bit SONOS (V4SONOS)  

Kim, Yoon (School of Electrical Engineering Seoul National University)
Yun, Jang-Gn (School of Electrical Engineering Seoul National University)
Cho, Seong-Jae (School of Electrical Engineering Seoul National University)
Park, Byung-Gook (School of Electrical Engineering Seoul National University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.47, no.2, 2010 , pp. 1-6 More about this Journal
Abstract
We proposed a highly integrated 3-dimensional NOR Flash memory array by using vertical 4-bit SONOS NOR flash memory. This structure has a vertical channel, so it is possible to have a long enough channel without extra cell area. Therefore, we can avoid second-bit effect, short channel effect, and redistribution of injected charges. And the proposed array structure is based on three-dimensional integration. Thus, we can obtain a NOR flash memory having $1.5F^2$/bit cell size.
Keywords
Charge Trap Flash; Multi-bit SONOS Flash Memory;
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1 Jang-Gn Yun, Yoon Kim, Il Han Park, Jung Hoon Lee, Sangwoo Kang, Dong-Hua Lee, Seongjae Cho, Doo-Hyun Kim, Gil Sung Lee, Won-Bo Sim, Younghwan Son, Hyungcheol Shin, Jong Duk Lee, and Byung-Gook Park, 'Fabrication and characterization of fin SONOS flash memory with separated double-gate structure,' Solid-State Electron., vol.52, pp.1498-1504, October. 2008   DOI   ScienceOn
2 Kinam Kim, 'The Future Prospect of Nonvolatile Memory', in Proc. VLSI-TSA 2005, pp.88-94, 2005   DOI
3 Chang Woo Oh, Na Young Kim, Sung Hwan Kim, Yong Lack Choi, Sung In Hong, Hyun Jun Bae, Jin Bum Kim, Kong Soo $Lee{^\ast},$ Yong Seok Lee, Nam Myun Cho, Dong-Won Kim, Donggun Park, and Byung-Il Ryu, '4-Bit Double SONOS Memories (DSMs) Using Single-Level and Multi-Level Cell Schemes,' in IEDM Tech. Dig., pp. 1-4, 2006   DOI
4 Jang-Gn Yun, Yoon Kim, Il Han Park, Jung Hoon Lee, Daewoong Kang, Myoungrack Lee, Hyungcheol Shin,Jong Duk Lee, and Byung-Gook Park, 'Independent Double-Gate Fin SONOS Flash Memory Fabricated With Sidewall Spacer Patterning,' IEEE Trans. Electron Dev., Vol.56, No. 8, pp. 1721-1728, Aug. 2009   DOI   ScienceOn
5 Seongjae Cho, Il Han Park, Jung Hoon Lee, Jang-Gn Yun, Doo-Hyun Kim, Jong Duk Lee, Hyungcheol Shin, and Byung-Gook Park, 'Establishing Read Operaion Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI),' IEICE Trans. Electron., Vol.E91-C, No.5, May, 2008
6 Eli Lusky, Yosi Shacham-Diamand, Gill Mitenberg, Assaf Shappir, Ilan Bloom, and BoazEitan,' Investigation of Channel Hot Electron Injection by Localized Charge-Trapping Nonvolatile Memory Devices,' IEEE TED. Vol.51, pp.444-451, Mar. 2004   DOI   ScienceOn
7 J. -W. Han, J. Lee, D. Park, and Y. -K. Choi, 'Body Thickness Dependence of Impact Ionization in a Multiple-Gate FinFET,' IEEE Electron Device Lett., vol. 28, No. 7, pp. 625-627, July. 2007   DOI   ScienceOn