• 한국항해항만학회:학술대회논문집
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• 한국항해항만학회 2005년도 추계학술대회 논문집
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• pp.125-131
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• 2005

게이트 운영은 수출 컨테이너를 위한 시작점이면서 수입 컨테이너의 종착점으로 컨테이너의 확인과 통제가 필요한 중요한 시설물이다. 본 연구의 목적은 컨테이너터미널 내부의 차량 통행량을 분산시키면서 차량의 체재시간을 감소시키기 위한 분리게이트 설계방안을 제안하는 것이다. 대량의 컨테이너가 단기간에 하역되기 때문에 많은 차량이 일시에 게이트를 통과해야 한다. 본 연구는 두개의 개별 선석의 통합을 고려한 게이트 운영을 위한 효과적인 설계로서 분리 게인트시스템을 제안한다.

• 한국항해항만학회지
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• 제30권5호
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• pp.389-396
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• 2006

최근의 항만 환경에서는 분리된 선석의 통합이 활발히 진행되고 있으며, 통합의 필요성도 높아지고 있다. 그러므로, 기존의 게이트들의 활용이 컨테이너터미널에서의 차량의 체재시간 감소와 차량 통행량 분산 측면에서 검토되어야 한다. 본 연구는 통합게이트와 분리게이트의 운영효과를 분석하였다. 본 연구는 두개의 개별 선석 통합시 게이트 운영의 효율성이 높은 분리게이트시스템을 제안한다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권2호
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• pp.156-163
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• 2008

We proposed a new $p^+/n^+$ gate locally-separated-channel (LSC) bulk FinFET which has vertically formed oxide region in the center of fin body, and device characteristics were optimized and compared with that of normal channel (NC) FinFET. Key device characteristics were investigated by changing length of $n^+$ poly-Si gate ($L_s$), the material filling the trench, and the width and length of the trench at a given gate length ($L_g$). Using 3-dimensional simulations, we confirmed that short-channel effects were properly suppressed although the fin width was the same as that of NC device. The LSC device having the trench non-overlapped with the source/drain diffusion region showed excellent $I_{off}$ suitable for sub-50 nm DRAM cell transistors. Design of the LSC devices were performed to get reasonable $L_s/L_g$ and channel fin width ($W_{cfin}$) at given $L_gs$ of 30 nm, 40 nm, and 50 nm.

• 한국전기전자재료학회논문지
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• 제36권6호
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• pp.609-613
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• 2023

In this paper, a 1,200 V Si-based IGBT used in electric vehicles and new energy industries was designed. A field stop IGBT with a separate gate structure, which is the proposed structure, was designed to change trench depth and split gate width variables. Then, the general trench structure and electrical characteristics were compared and analyzed. As a result of conducting the trench depth experiment, it was confirmed that the breakdown voltage was the highest at 6 ㎛, and the on-state voltage drop was the lowest at 3.5 ㎛. In the separate gate width experiment, it was confirmed that the breakdown voltage decreased as the variable increased, and the on-state voltage drop increased. Therefore, it may be seen that it is preferable not to change the width of the separate gate. In addition, experiments show that there is no difference in on-state voltage drop compared to a structure in which a general field stop structure has a separate gate structure. In other words, it is determined that adding a dummy gate with a separate gate structure to the active cell will significantly improve the on-voltage drop characteristics, while confirming that the on-voltage drop does not change, and while having excellent characteristics in terms of breakdown voltage.

• Journal of information and communication convergence engineering
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• 제10권1호
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• pp.1-4
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• 2012

Given separated points divided by a line, called a wall, in a plane, we aim to make a gate in the wall to connect the separated points to each other. In this setting, the problem is to find a location for the gate that minimizes the average distance between the points. The problem is a variant of the well-known facility location problem, which is extensively studied in the fields of operations research, location theory, theoretical computer science, and so on. In this paper, we consider the $L^1$-distance of the points in the plane. The points are projected onto the wall and so the problem is transformed to a proximity problem of points on a line. Then it is shown that the transformed problem is related to the weighted median problem of points on the line. Therefore, we obtain an O(n log n)-time algorithm to solve our problem.

• 한국컴퓨터산업학회논문지
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• 제6권5호
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• pp.783-790
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• 2005

In this paper, we have simulated a Symmetric Dual-gate Single-Si TFT which has three split floating n+ zones. This structure reduces the kink-effect drastically and improves the on-current. Due to the separated floating n+ zones, the transistor channel region is split into four zones with different lengths defined by a floating n+ region, This structure allows an effective reduction of the kink-effect depending on the length of two sub-channels. The on-current of the proposed dual-gate structure is 0.9mA while that of the conventional dual-gate structure is 0.5mA at a 12V drain voltage and a 7V gate voltage. This result shows a 80% enhancement in on-current. Moreover we observed the reduction of electric field in the channel region compared to conventional single-gate TFT and the reduction of the output conductance in the saturation region. In addition, we also confirmed the reduction of hole concentration in the channel region so that the kink-effect reduces effectively.

• 센서학회지
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• 제16권4호
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• pp.313-318
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• 2007

Single-wall carbon nanotube field-effect transistors (SWCNT FETs) of top gate structure were fabricated in a conventional metal-oxide-semiconductor field effect transistor (MOSFET) with gate electrodes above the conduction channel separated from the channel by a thin $SiO_{2}$ layer. The carbon nanotubes (CNTs) directly grown using thin Fe film as catalyst by thermal chemical vapor deposition (CVD). These top gate devices exhibit good electrical characteristics, including steep subthreshold slope and high conductance at low gate voltages. Our experiments show that CNTFETs may be competitive with Si MOSFET for future nanoelectronic applications.

• 한국신뢰성학회지:신뢰성응용연구
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• 제10권1호
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• pp.65-71
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• 2010

NAND-type SONOS with a separated double-gate FinFET structure (SDF-Fin SONOS) flash memory devices are proposed to reduce the unit cell size of the memory device and increase the memory density in comparison with conventional non volatile memory devices. The proposed memory device consists of a pair of control gates separated along the direction of the Fin width. There are two unique alternative technologies in this study. One is a channel doping method and the other is an oxide thickness variation method, which are used to operate the SDF-Fin SONOS memory device as two-bit. The fabrication processes and the device characteristics are simulated by using technology comuter-adided(TCAD). The simulation results indicate that the charge trap probability depends on the different channel doping concentration and the tunneling oxide thickness. The proposed SDG-Fin SONOS memory devices hold promise for potential application.

• Transactions on Electrical and Electronic Materials
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• 제7권2호
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• pp.53-57
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• 2006

In this paper, a Symmetric Dual-gate Single-Si TFT, which includes three split floating n+ zones, is simulated. This structure drastically reduces the kink-effect and improves the on-current. This is due to the separated floating n+ zones, the transistor channel region is split into four zones with different lengths defined by a floating n+ region. This structure allows effective reduction in the kink-effect, depending on thy length of the two sub-channels. The on-current of the proposed dual-gate structure is 0.9 mA, while that of the conventional dual-gate structure is 0.5 mA, at both 12 V drain and 7 V gate voltages. This result shows an 80% enhancement in on-current. In addition, the reduction of electric field in the channel region compared to a conventional single-gate TFT and the reduction of the output conductance in the saturation region, is observed. In addition, the reduction in hole concentration, in the channel region, in order for effectively reducing the kink-effect, is also confirmed.

• 한국전기전자재료학회논문지
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• 제18권5호
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• pp.423-430
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• 2005

In this paper, we have simulated a Symmetric Dual-gate Single-Si TFT which has three split floating $n^{+}$ zones. This structure reduces the kink-effect drastically and improves the on-current. Due to the separated floating $n^{+}$ zones, the transistor channel region is split into four zones with different lengths defined by a floating $n^{+}$ region. This structure allows an effective reduction of the kink-effect depending on the length of two sub-channels. The on-current of the proposed dual-gate structure is 0.9 mA while that of the conventional dual-gate structure is 0.5 mA at a 12 V drain voltage and a 7 V gate voltage. This results show a $80 {\%}$ enhancement in on-current by adding two floating $n^{+}$ zones. Moreover we observed the reduction of electric field In the channel region compared to conventional single-gate TFT and the reduction of the output conductance in the saturation region. In addition we also confirmed the reduction of hole concentration in the channel region so that the kink-effect reduces effectively.