[KSCI] Korea Science Citation Index Service

Nanoscale NAND SONOS memory devices including a Seperated double-gate FinFET structure

Kim, Hyun-Joo (Dept. of Information Display, Hanyang University)
Kim, Kyeong-Rok (Dept. of Nanoscale Semiconductor Engineering, Hanyang University)
Kwack, Kae-Dal (Dept. of Information Display, Hanyang University)

Publication Information

Journal of Applied Reliability / v.10, no.1, 2010 , pp. 65-71 More about this Journal

Abstract

NAND-type SONOS with a separated double-gate FinFET structure (SDF-Fin SONOS) flash memory devices are proposed to reduce the unit cell size of the memory device and increase the memory density in comparison with conventional non volatile memory devices. The proposed memory device consists of a pair of control gates separated along the direction of the Fin width. There are two unique alternative technologies in this study. One is a channel doping method and the other is an oxide thickness variation method, which are used to operate the SDF-Fin SONOS memory device as two-bit. The fabrication processes and the device characteristics are simulated by using technology comuter-adided(TCAD). The simulation results indicate that the charge trap probability depends on the different channel doping concentration and the tunneling oxide thickness. The proposed SDG-Fin SONOS memory devices hold promise for potential application.

Keywords

NAND-type SONOS; SDF-Fin SONOS; Memory devices; Oxide thickness variation method; TCAD;

Citations & Related Records

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