• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.3
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• pp.195-203
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• 2005

Recently, a novel multi-bit nonvolatile memory based on double gate (DG) MOSFET is proposed to overcome the short channel effects and to increase the memory density. We need more complex voltage schemes for DG MOSFET devices. In view of peripheral circuits driving memory cells, one should consider various voltage sources used for several operations. It is one of the key issues to minimize the number of voltage sources. This criterion needs more caution in considering a DG nonvolatile memory cell that inevitably requires more number of events for voltage sources. Therefore figuring out the permissible range of operating bias should be preceded for reliable operation. We found that reliable operation largely depends on the depletion conditions of the silicon channel according to charge amount stored in the floating gates and the negative control gate voltages applied for read operation. We used Silvaco Atlas, a 2D numerical simulation tool as the device simulator.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.1
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• pp.12-16
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• 2009

Current sensing in power semiconductors involves sensing of over-current in order to protect the device from harsh conditions. This technique is one of the most important functions in stabilizing power semiconductor device modules. The sense FET is very efficient method with low power consumption, fast sensing speed and accuracy. In this paper, we have analyzed the characteristics of proposed sense FET and optimized its electrical characteristics to apply conventional 450 V power MOSFET by numerical and simulation analysis. The proposed sense FET has the n-drift doping concentration $1.5{\times}10^{14}cm^{-3}$, size of $600{\um}m^2$ with $4.5\;{\Omega}$, and off-state leakage current below $50{\mu}A$. We offer the layout of the proposed sense FET to process actually. The offerd design and optimization methods are meaningful, which the methods can be applied to the power devices having various breakdown voltages for protection.

• Journal of the Korea institute for structural maintenance and inspection
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• v.23 no.7
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• pp.40-48
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• 2019

New concept of fine dust measurement method is suggested based on ultrasonic scattering. These days, fine dust has been social problem in Korea, and many researches has been conducted including the area structural maintenance. Conventional measurement system such as optical scattering and semiconductor has a limit from environmental factors like relative humidity. However, ultrasound is based on mechanical waves, which perturb mechanical properties of medium such as density and elastic constants. Using the advantage, the algorithm for fine dust measurement is derived and evaluated using 2-D finite difference method. The numerical analysis simulates ultrasonic wave propagation inside multiple scattering medium like fine dust in air. Signal processing scheme is also suggested and the results show that the error of the algorithm is around minimum of 0.7 and maximum of 24.9 in the number density unit. It is shown that cross-section of fine dust is a key parameter to improve the accuracy of algorithm.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.39 no.10
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• pp.1011-1019
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• 2015

Insulated-gate bipolar transistors (IGBTs) are the predominantly used power semiconductors for high-current applications, and are used in trains, airplanes, electrical, and hybrid vehicles. IGBT power modules generate a considerable amount of heat from the dissipation of electric power. This heat generation causes several reliability problems and deteriorates the performances of the IGBT devices. Therefore, thermal management is critical for IGBT modules. In particular, realizing a proper thermal design for which the device temperature does not exceed a specified limit has been a key factor in developing IGBT modules. In this study, we investigate the thermal behavior of the 1200 A, 3.3 kV IGBT module package using finite-element numerical simulation. In order to minimize the temperature of IGBT devices, we analyze the effects of various packaging materials and different thickness values on the thermal characteristics of IGBT modules, and we also perform a design-of-experiment (DOE) optimization

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.7
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• pp.16-25
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• 2002

This paper presents a methodology and application for extracting parasitic inductances in a multi-level interconnect semiconductor structure by a numerical technique. In order to calculate the parasitic inductances, the distrubution of electric potential and current density in the metal lines are calculated by finite element method (FEM). Thereafter, the magneto-static energy caused by the current density in metal lines was calculated. The result of simulation is compared with the result of Grover equation about analytic simple structures, and 4 bit ROM array with a dimension of $13{\times}10.25{\times}8.25{\mu}m^3$ was simulated to extract the parasitic inductnaces. In this calculation, 6,358 nodes with 31,941 tetrahedra were used in ULTRA 10 workstation. The total CPU time for the simulation was about 150 seconds, while the memory size of 20 MB was required.

• Particle and aerosol research
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• v.18 no.4
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• pp.129-136
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• 2022

The line width of circuits in semiconductor devices continues to decrease down to a few nanometers. Since nanoparticles attached to the patterned wafer surface may cause malfunction of the devices, it is crucial to remove the contaminant nanoparticles. Physical cleaning that utilizes momentum of liquid for detaching solid nanoparticles has recently been tested in place of the conventional chemical method. Dropwise impaction has been employed to increase the removal efficiency with expectation of more efficient momentum exchange. To date, most of relevant studies have been focused on drop spreading behavior on a horizontal surface in terms of maximum spreading diameters and average spreading velocity of drop. More important is the local liquid velocity at the position of nanoparticle, very near the surface, rather than the vertical average value. In addition, there are very scarce existing studies dealing with microdroplet impaction that may be desirable for minimizing pattern demage of the wafer. In this study, we investigated the local velocity distribution in spreading liquid film under various impaction conditions through the CFD simulation. Combining the numerical results with the particle removal model, we estimated an effective cleaning diameter (ECD), which is a measure of the particle removal capacity of a single drop, and presented the predicted ECD data as a function of droplet's velocity and diameter particularly when the droplets are microns in diameter.

• Nanomaterials
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• v.12 no.5
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• pp.827-838
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• 2022

Controlling the Schottky barrier height (φ_B) and other parameters of Schottky barrier diodes (SBD) is critical for many applications. In this work, the effect of inserting a graphene interfacial monolayer between a Ni Schottky metal and a β-Ga₂O₃ semiconductor was investigated using numerical simulation. We confirmed that the simulation-based on Ni workfunction, interfacial trap concentration, and surface electron affinity was well-matched with the actual device characterization. Insertion of the graphene layer achieved a remarkable decrease in the barrier height (φ_B), from 1.32 to 0.43 eV, and in the series resistance (R_s), from 60.3 to 2.90 mΩ.cm². However, the saturation current (J_s) increased from 1.26×10^-11 to 8.3×10^-7(A/cm²). The effects of a graphene bandgap and workfunction were studied. With an increase in the graphene workfunction and bandgap, the Schottky barrier height and series resistance increased and the saturation current decreased. This behavior was related to the tunneling rate variations in the graphene layer. Therefore, control of Schottky barrier diode output parameters was achieved by monitoring the tunneling rate in the graphene layer (through the control of the bandgap) and by controlling the Schottky barrier height according to the Schottky-Mott role (through the control of the workfunction). Furthermore, a zero-bandgap and low-workfunction graphene layer behaves as an ohmic contact, which is in agreement with published results.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.4
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• pp.49-60
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• 2010

Semiconductor packages are increasingly moving toward miniaturization, lighter and high performance. Futhermore, packages become thinner. Thin packages will generate serious reliability problems such as warpage, crack and other failures. Reliability problems are mainly caused by the CTE mismatch of various package materials. Therefore, proper selection of the package materials and geometrical optimization is very important for controlling the warpage and the stress of the package. In this study, we investigated the characteristics of the warpage and the stress of several packages currently used in mobile devices such as CABGA, fcSCP, SCSP, and MCP. Warpage and stress distribution are analyzed by the finite element simulation. Key material properties which affect the warpage of package are investigated such as the elastic moduli, CTEs of EMC molding and the substrate. Geometrical effects are also investigated including the thickness or size of EMC molding, silicon die and substrate. The simulation results indicate that the most influential factors on warpage are EMC molding thickness, CTE of EMC, elastic modulus of the substrate. Simulation results show that warpage is the largest for SCSP. In order to reduce the warpage, DOE optimization is performed, and the optimization results show that warpage of SCSP becomes $10{\mu}m$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.615-624
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• 2014

In this paper, we explore the electrical properties and high-frequency performance of carbon nanotube field-effect transistors (CNTFETs), based on the non-equilibrium Green's functions (NEGF) solved self - consistently with Poisson's equations. The calculated results show that CNTFETs exhibit superior performance compared with graphene nanoribbon field-effect transistors (GNRFETs), such as better control ability of the gate on the channel, higher drive current with lower subthreshold leakage current, and lower subthreshold-swing (SS). Due to larger band-structure-limited velocity in CNTFETs, ballistic CNTFETs present better high-frequency performance limit than that of Si MOSFETs. The parameter effects of CNTFETs are also investigated. In addition, to enhance the immunity against short - channel effects (SCE), hetero - material - gate CNTFETs (HMG-CNTFETs) have been proposed, and we present a detailed numerical simulation to analyze the performances of scaling down, and conclude that HMG-CNTFETs can meet the ITRS'10 requirements better than CNTs.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.5
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• pp.44-53
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• 1999

This paper are reported a methodology and application for extracting parasitic capacitances in a multi-level interconnect semiconductor structure by a numerical technique. To calculate the parasitic capacitances between the interconnect lines, we employed finite element method (FEM) and calculated the distrubution of electric potential in the inter-metal layer dielecric(ILD) by solving the Laplace equation. The three-dimensional multi-level interconnect structure is generated directly from two-dimensional mask layout data by specifying process sequences and dimension. An exemplary structure comprising two metal lines with a dimension of 8.0$\times$8.0$\times$5.0$\mu\textrm{m}^3/TEX>, which is embedded in three dielectric layer, was simulated to extract the parasitic capacitances. In this calculation, 1960 nodes with 8892 tetrahedra were used in ULTRA SPARC 1 workstation. The total CPU time for the simulation was 28 seconds, while the memory size of 4.4MB was required.