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A Study on the Extraction of Parasitic Inductance for Multiple-level Interconnect Structures  

Yoon, Suk-In (School of Electrical Engineering, Inha University)
Won, Tae-Young (School of Electrical Engineering, Inha University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.39, no.7, 2002 , pp. 16-25 More about this Journal
Abstract
This paper presents a methodology and application for extracting parasitic inductances in a multi-level interconnect semiconductor structure by a numerical technique. In order to calculate the parasitic inductances, the distrubution of electric potential and current density in the metal lines are calculated by finite element method (FEM). Thereafter, the magneto-static energy caused by the current density in metal lines was calculated. The result of simulation is compared with the result of Grover equation about analytic simple structures, and 4 bit ROM array with a dimension of $13{\times}10.25{\times}8.25{\mu}m^3$ was simulated to extract the parasitic inductnaces. In this calculation, 6,358 nodes with 31,941 tetrahedra were used in ULTRA 10 workstation. The total CPU time for the simulation was about 150 seconds, while the memory size of 20 MB was required.
Keywords
Inductance; Interconnect; Parasitics; FEM;
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