JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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Quantitative Analysis on Voltage Schemes for Reliable Operations of a Floating Gate Type Double Gate Nonvolatile Memory Cell

  • Cho, Seong-Jae (School of Electrical Engineering and Computer Science, Seoul National University) ;
  • Park, Il-Han (School of Electrical Engineering and Computer Science, Seoul National University) ;
  • Kim, Tae-Hun (School of Electrical Engineering and Computer Science, Seoul National University) ;
  • Lee, Jung-Hoon (School of Electrical Engineering and Computer Science, Seoul National University) ;
  • Lee, Jong-Duk (School of Electrical Engineering and Computer Science, Seoul National University) ;
  • Shin, Hyung-Cheol (School of Electrical Engineering and Computer Science, Seoul National University) ;
  • Park, Byung-Gook (School of Electrical Engineering and Computer Science, Seoul National University)
  • Published : 2005.09.30
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Abstract

Recently, a novel multi-bit nonvolatile memory based on double gate (DG) MOSFET is proposed to overcome the short channel effects and to increase the memory density. We need more complex voltage schemes for DG MOSFET devices. In view of peripheral circuits driving memory cells, one should consider various voltage sources used for several operations. It is one of the key issues to minimize the number of voltage sources. This criterion needs more caution in considering a DG nonvolatile memory cell that inevitably requires more number of events for voltage sources. Therefore figuring out the permissible range of operating bias should be preceded for reliable operation. We found that reliable operation largely depends on the depletion conditions of the silicon channel according to charge amount stored in the floating gates and the negative control gate voltages applied for read operation. We used Silvaco Atlas, a 2D numerical simulation tool as the device simulator.

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References

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