Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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A Study on the Extraction of Parasitic Inductance for Multiple-level Interconnect Structures

다층배선 인터커넥트 구조의 기생 인덕턴스 추출 연구

  • Yoon, Suk-In (School of Electrical Engineering, Inha University) ;
  • Won, Tae-Young (School of Electrical Engineering, Inha University)
  • 윤석인 (仁荷大學校 電子電氣工學部) ;
  • 원태영 (仁荷大學校 電子電氣工學部)
  • Published : 2002.07.01
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Abstract

This paper presents a methodology and application for extracting parasitic inductances in a multi-level interconnect semiconductor structure by a numerical technique. In order to calculate the parasitic inductances, the distrubution of electric potential and current density in the metal lines are calculated by finite element method (FEM). Thereafter, the magneto-static energy caused by the current density in metal lines was calculated. The result of simulation is compared with the result of Grover equation about analytic simple structures, and 4 bit ROM array with a dimension of $13{\times}10.25{\times}8.25{\mu}m^3$ was simulated to extract the parasitic inductnaces. In this calculation, 6,358 nodes with 31,941 tetrahedra were used in ULTRA 10 workstation. The total CPU time for the simulation was about 150 seconds, while the memory size of 20 MB was required.

본 논문에서는 반도체 집적 회로의 다층 배선 인터커넥트 사이의 기생 인덕턴스를 수치 해석적으로 계산하여 추출하는 방법과 그 적용 예를 보고한다. 기생 인덕턴스를 추출하기 위하여, 3차원 다층배선 구조물에 대해 유한요소법을 이용하여 다층 배선내에서의 전위 분포 및 전류 밀도를 계산하고, 계산된 전류 밀도로부터 자계 에너지를 계산하여 상호 인덕턴스 및 셀프 인덕턴스를 계산하였다. 시뮬레이션 결과의 정확도를 검증하기 위하여 해석적 방법으로 해석이 가능한 간단한 구조에 대하여 시뮬레이션을 수행하여 결과를 비교하였으며, 또다른 응용으로, $13{\times}10.25{\times}8.25\;{\mu}m^3$ 크기의 4비트 룸 구조에 대하여 시뮬레이션을 수행하였다. 3차원 4비트 룸 구조물의 기생 인덕턴스 추출을 위해서, 유한요소법 적용을 위한 6,358개의 노드와 31,941개의 사면체 메쉬를 생성하였으며, ULTRA 10 워크스테이션에 대해서 소요된 CPU 시간은 약 2분 30초이었으며, 20 메가바이트의 메모리를 사용하였다.

Keywords

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