• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.1
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• pp.199-202
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• 2009

Scan design is currently the most widely used structured Design For Testability approach. In scan design, all storage elements are replaced with scan cells, which are then configured as one or more shift registers(also called scan chains) during the shift operation. As a result, all inputs to the combinational logic, including those driven by scan cells, can be controlled and all outputs from the combinational logic, including those driving scan cells, can be observed. The scan inserted design, called scan design, is operated in three modes: normal mode, shift mode, and capture mode. Circuit operations with associated clock cycles conducted in these three modes are referred to as normal operation, shift operation, and capture operation, respectively. In spite of these, scan design methodology has defects. They are power dissipation problem and test time during test application. We propose a new methodology about scan shift clock operation and present low power scan design and short test time.

• ETRI Journal
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• v.38 no.3
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• pp.479-486
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• 2016

System-on-chip (SoC) designs have a number of flip-flops; the more flip-flops an SoC has, the longer the associated scan test application time will be. A scan shift operation accounts for a significant portion of a scan test application time. This paper presents physical-aware approaches for speeding up scan shift operations in SoCs. To improve the speed of a scan shift operation, we propose a layout-aware flip-flop insertion and scan shift operation-aware physical implementation procedure. The proposed combined method of insertion and procedure effectively improves the speed of a scan shift operation. Static timing analyses of state-of-the-art SoC designs show that the proposed approaches help increase the speeds of scan shift operations by up to 4.1 times that reached under a conventional method. The faster scan shift operation speeds help to shorten scan test application times, thus reducing test costs.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.7
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• pp.458-461
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• 2005

Power dissipated during test application is substantially higher than power dissipated during functional operation which can decrease the reliability and lead to yield loss. This paper presents a new technique for power minimization during test application in full scan sequential circuits. This paper shows freezing of combinational logic parts during scan shift operation in test mode. The freezing technique leads to power to minimization. Significant power reduction in the scan techniques is achieved on ISCAS 89 benchmarks.

• The Korean Journal of Nuclear Medicine Technology
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• v.19 no.2
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• pp.63-67
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• 2015

Purpose Among various causes that influence image quality degradation, various methods for decrease in Artifact occurred by respiration of patients are being used. Among them, this study intended to evaluate CTAC Shift correction method and additional scan compare to the Scan(Q static scan) using respiratory gated system. Materials and Methods This study was conducted on 10 patients, and used PET-CT Discovery 710 (GE Healthcare, MI, USA) and Varian's RPM system. 5.18 Mbq per kg of $^{18}F$-FDG was injected on patients, asked them to take a rest for 1 hour in the bed, and conducted test after urination. Images were visualized through Q static scan, CTAC Shift correction method, Additional scan based on the Whole body scan(WBS) with Artifact. Decrease in Artifact was compared in each image, conducted Gross Evalution, and measured changes of SUVmax. Results For image obtained through the CTAC Shift correction method through WBS with Artifact, 12~56%, Q static scan image showed 17~54% of change rate and Additional Scan showed -27~46% of change rate. In Blind Test, the CTAC Shift correction image showed the highest point with 4 points, Q static scan image showed 3.5 points, and Additional scan image showed 3.4 points. The standardized WBS scan through Oneway ANOVA and three types of Scan method showed significant difference(p<0.05), and did not show significant difference between the three Scan methods(p>0.05). However, the three Scan methods showed significant difference in Blind test. Conclusion Additional scan and Q static scan require more time than the CTAC Shift correction method, there is concern about excessive exposure to patients by CT rescan and Q static scan is difficult to apply on patients with inconsistent respiration or irregular respiration cycle due to pain. For CTAC Shift correction method, limited correction is possible and the range is limited as well. It is considered as a useful method of improving diagnostic value when hospitals use the system appropriately and develop various advantageous factors of each method.

• KIEE International Transactions on Electrophysics and Applications
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• v.3C no.6
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• pp.246-251
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• 2003

We report the theory of thin-sample Z -scan for materials, viz. diffusion-dominated photorefractives, having a nonlinearly induced phase that may be proportional to the spatial derivative of the intensity profile. The on-axis far-field intensity is approximately an even function of the scan distance on different positive and negative values for phase shift $\Delta$$\Phi$$_{o}$. In case of positive phase shift, the Z -scan graph shows a minimum and two maxima, while for the negative value, only one minimum is observed. The fact is that far-field beam profiles display beam distortion and shift of the peak as compared with Kerr-type or photovoltaic nonlinearities.s.

• Journal of Electrical Engineering and Technology
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• v.4 no.4
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• pp.559-565
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• 2009

Power dissipation during scan testing is becoming an important concern as design sizes and gate densities increase. The high switching activity of combinational circuits is an unnecessary operation in scan shift mode. In this paper, we present a novel architecture to reduce test power dissipation in combinational logic by blocking signal transitions at the logic inputs during scan shifting. We propose a unique architecture that uses dmuxed scan flip-flop (DSF) and transmission gate as an alternative to muxed scan flip-flop. The proposed method does not have problems with auto test pattern generation (ATPG) techniques such as test application time and computational complexity. Moreover, our elegant method improves performance degradation and large overhead in terms of area with blocking logic techniques. Experimental results on ITC99 benchmarks show that the proposed architecture can achieve an average improvement of 30.31% in switching activity compared to conventional scan methods. Additionally, the results of simulation with DSF indicate that the powerdelay product (PDP) and area overhead are improved by 28.9% and 15.6%, respectively, compared to existing blocking logic method.

• The Korean Journal of Nuclear Medicine Technology
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• v.17 no.1
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• pp.71-75
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• 2013

Purpose: Currently, decrement revision using LDCT is used in PET/CT. But cold artifacts are often found in decrement revision image by mismatch between LDCT image and Emission image near diaphragm due to patient's respiration. This research studied reduction of cold artifact by patient's respiration using CTAC Shift among revision methods. Materials and Methods: From March to September in 2012, 30 patients who had cold artifacts by respiration were targeted using PET/CT Discovery 600 (GE Healthcare, MI, USA) equipment. Patients with cold artifacts were additionally scan in diaphragm area, and the image shown cold artifacts at whole body test were revised using CTAC Shift. Cold artifacts including image, additional scan image and CTAC Shift revision image were evaluated as 1~5 points with naked eye by one nuclear medicine expert, 4 radiotechnologists with over 5 year experience. Also, standard uptake value of 3 images was compared using paired t-test. Results: Additional scan image and CTAC Shift revision image received relatively higher score in naked eye evaluation than cold artifacts including image. The additional scan image and CTAC Shift revision image had high correlation as the results of ANOVA test of standard uptake value and did not show significant difference. Conclusion: When cold artifacts are appeared by patient's respiration at PET/CT, it causes not only patient inconvenience but troubles in test schedule due to extra radiation exposure and time consumption by additional scan. But if CTAC Shift revision image can be acquired with out additional scan, it is considered to be helped in exact diagnosis without unnecessary extra radiation exposure and additional scan.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.10
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• pp.45-51
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• 2003

In this paper, a scan-based low power BIST (Built-In Self-Test) architecture is proposed. The proposed architecture is based on STUMPS, which uses a LFSR (Linear Feedback Shift Register) as the test generator, a MISR(Multiple Input Shift Register) as the reponse compactor, and SRL(Shift Register Latch) channels as multiple scan paths. In the proposed BIST a degenerate MISR structure is used for every SRL channel; this offers reduced area overheads and has less impact on performance than the STUMPS techniques. The proposed BIST is designed to support both test-per-clock and test-per-scan techniques, and in test-per-scan the total power consumption of the circuit can be reduced dramatically by suppressing the effects of scan data on the circuits. Results of the experiments on ISCAS 89 benchmark circuits show that this architecture is also suitable for detecting path delay faults, when the hamming distance of the data in the SRL channel is considered.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.14 no.4
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• pp.219-225
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• 2014

The New efficient Mux-based scan latch cell design and scan test of LOS/LOC modes are proposed for detection of delay faults in digital logic circuits. The proposed scan cell design can support LOS(Launch-off-Shift) and LOC(Launch-off-Capture) tests with high fault coverage and low scan power and it can alleviate the problem of the slow selector enable signal and hold signal by supporting the logic capable of switching at the operational clock speeds. Also, it efficiently controls the power dissipation of the scan cell design during scan testing. Functional operation and timing simulation waveform for proposed scan hold cell design shows improvement in at-speed test timing in both test modes.

• Journal of Electrical Engineering and Technology
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• v.3 no.1
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• pp.130-134
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• 2008

The increasing size of very large scale integration (VLSI) circuits, high transistor density, and popularity of low-power circuit and system design are making the minimization of power dissipation an important issue in VLSI design. Test Power dissipation is exceedingly high in scan based environments wherein scan chain transitions during the shift of test data further reflect into significant levels of circuit switching unnecessarily. Scan chain or cell modification lead to reduced dissipations of power. The ETC algorithm of previous work has weak points. Taking all of this into account, we therefore propose a new algorithm. Its name is RE_ETC. The proposed modifications in the scan chain consist of Exclusive-OR gate insertion and scan cell reordering, leading to significant power reductions with absolutely no area or performance penalty whatsoever. Experimental results confirm the considerable reductions in scan chain transitions. We show that modified scan cell has the improvement of test efficiency and power dissipations.