• Electrical & Electronic Materials
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• v.7 no.2
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• pp.123-129
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• 1994

SONOS EEPROM chips, containing several SONOSFET nonvolatile memories of various channel size, have been fabricated on the basis of the existing n-well CMOS processing technology for 1 Mbit DRAM ($1.2\mu\textrm{m}$.m design rule). All the SONOSFET memories have the triple insulated-gate consisting of 30.angs. tunneling oxide, 205.angs. nitride and 65.angs. blocking oxide. The miniaturization of the devices for the higher density EEPROM and their characteristics alterations accompanied with the scaling-down have been investigated. The stabler operating characteristics were attained by increasing the ratio of the channel width to length. Also, the transfer, switching, retention and degradation characteristics of the most favorable performance devices were presented and discussed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.119-119
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• 2008

The electrical characteristics of Metal-Ferroelectric-Nitride-Oxide-Silicon (MFNOS) structure is studied and compared to the conventional Silicon-Oixde-Nitride-Oxide-Silicon (SONOS) capacitor. The ferroelectric blocking layer is SrBiNbO (SBN with Sr/Bi ratio 1-x/2+x) with the thickness of 200 nm and is fabricated by the RF sputter. The memory windows of MFNOS and SONOS capacitors with sweep voltage from +10 V to -10 V are 6.9 V and 5.9 V, respectively. The effect of ferroelectric blocking layer and charge trapping on the memory window was discussed. The retention of MFNOS capacitor also shows the 10-years and longer retention time than that of the SONOS capacitor. The better retention properties of the MFNOS capacitor may be attributed to the charge holding effect by the polarization of ferroelectric layer.

• Transactions on Electrical and Electronic Materials
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• v.12 no.1
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• pp.16-19
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• 2011

The oxide-nitride-oxide (ONO) deposition process was added to the beginning of a 0.25 ${\mu}m$ embedded polysiliconoxide-nitride-oxide-silicon (SONOS) process before all of the logic well implantation processes in order to maintain the characteristics of basic CMOS(complementary metal-oxide semiconductor) logic technology. The system subsequently suffered severe ONO rupture failure. The damage was caused by the ONO implantation and was responsible for the ONO rupture failure in the embedded SONOS process. Furthermore, based on the experimental results as well as an implanted ion's energy loss model, processes primarily producing permanent displacement damages responsible for the ONO rupture failure were investigated for the embedded SONOS process.

• Transactions on Electrical and Electronic Materials
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• v.7 no.4
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• pp.180-183
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• 2006

We report for the first time two-bit operational characteristics of a high-density NOR-type polysilicon-oxide-nitride-oxide-silicon (SONOS) array with common source line (CSL). An undesired disturbance, especially drain disturbance, in the NOR array with CSL comes from the two-bit-per-cell operation. To solve this problem, we propose an efficient bulk-biased programming technique. In this technique, a bulk bias is additionally applied to the substrate of memory cell for decreasing the electric field between nitride layer and drain region. The proposed programming technique shows free of drain disturbance characteristics. As a result, we have accomplished reliable two-bit SONOS array by employing the proposed programming technique.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.6
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• pp.409-413
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• 2012

In this study, a substrate-bias assisted 2-step pulse programming method is proposed for realizing 4-bit/1-cell operation of the SONOS memory. The programming voltage and time are considerably reduced by this programming method than a gate-bias assisted 2-step pulse programming method and CHEI method. It is confirmed that the difference of 4-states in the threshold voltage is maintained to more than 0.5 V at least for 10-year for the multi-level characteristics.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.80-83
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• 2003

In this paper, the programming characteristics of the multi-bit devices based on SONOS structure are investigated. Our devices have been fabricated by $0.35\;{\mu}m$ complementary metal-oxide-semiconductor (CMOS) process with LOCOS isolation. In order to achieve the two-bits per cell operation, charges must be locally trapped in the nitride layer above the channel near the junction. Channel hot electron (CHE) injection for programming can operate in multi-bit using localized trap in nitride film. CHE injection in our devices is achieved with the single power supply of 5 V. To demonstrate CHE injection, substrate current (Isub) and one-shot programming curve were investigated. The multi-bit operation which stores two-bit per cell is investigated with a reverse read scheme. Also, hot hole injection for fast erasing is used. Due to the ultra-thin gate dielectrics, our results show many advantages which are simpler process, better scalability and lower programming voltage compared to any other two-bit storage flash memory. This fabricated structure and programming characteristics are shown to be the most promising for the multi-bit flash memory.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.214-214
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• 2010

단위면적 당 메모리 집적도를 높이기 위해 플래시 기억소자의 크기를 줄일 때, 셀 사이의 거리의 감소에 의한 간섭효과가 매우 커져 소자 크기의 축소가 한계에 도달하고 있다. 이러한 문제점을 개선하기 위해 본 연구에서는 fringing field 효과를 이용한 SONOS 구조 게이트 위에 금속 공간층을 가지는 플래시 메모리 소자를 연구하였다. 소자에 소스와 드레인에 도핑을 하는 공정단계를 거치지 않아도 되는 fringing field 효과를 이용한 SONOS 구조를 가진 기억소자에서 트랩층 양 쪽에 절연막을 증착하고 게이트 외측으로부터 트랩층 양 쪽 절연막까지 금속을 증착시켜 금속 공간층을 형성하였다. 게이트에 전압을 인가할 때 트랩층 절연막 외측의 금속 공간층 영역에도 동시에 전압이 인가되므로 게이트가 스위칭 역할을 충분히 하게 하기 위해서 트랩층 양 쪽 절연막 두께를 블로킹 산화막 두께와 같게 하였다. 소자의 누설전류를 감소하기 위하여 채널 아래 부분에 boron으로 halo 도핑을 하였다. 제안한 기억소자가 fringing field 효과에 의해 동작하는 것을 확인하기 위하여 Sentaurus를 사용하여 제시한 SONOS 구조를 가진 기억소자의 전기적 특성을 조사하였다. 시뮬레이션을 통해 얻은 금속 공간층이 있을 때와 없을 때에 대한 각 상태에서 같은 조건으로 트랩층에 전하를 트랩 시켰을 때 포획된 전하량이 변하였다. 각 상태에서 제어게이트에 읽기 전압을 인가하여 전류-전압 특성 곡선을 얻었으며, 각 상태에서의 문턱전압의 변화를 통해 금속 공간층이 있을 때 간섭효과가 감소하였다.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.331-331
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• 2012

With the NAND Flash scaling down, it becomes more and more difficult to follow Moore's law to continue the scaling due to physical limitations. Recently, three-dimensional (3D) flash memories have introduced as an ideal solution for ultra-high-density data storage. In 3D flash memory, as the process reason, we need to use poly-Si TFTs instead of conventional transistors. So, after combining charge trap flash (CTF) structure and poly-Si TFTs, the emerging device SONOS-TFTs has also suffered from some reliability problem such as hot carrier degradation, charge-trapping-induced parasitic capacitance and resistance which both create interface traps. Charge pumping method is a useful tool to investigate the degradation phenomenon related to interface trap creation. However, the curves for charge pumping current in SONOS TFTs were far from ideal, which previously due to the fabrication process or some unknown traps. It needs an optimization and the important geometrical effect should be eliminated. In spite of its importance, it is still not deeply studied. In our work, base-level sweep model was applied in SONOS TFTs, and the nonideal charge pumping current was optimized by adjusting the gate pulse transition time. As a result, after the optimizing, an improved charge pumping current curve is obtained.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.12
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• pp.1017-1021
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• 2007

To implement tera bit level non-volatile memories of low power and fast operation, proving statistical reproductivity and satisfying reliabilities at the nano-scale are a key challenge. We fabricate the charge trapping nano scaled SONOS unit memories and 64 bit flash arrays and evaluate reliability and performance of them. In case of the dielectric stack thickness of 4.5 /9.3 /6.5 nm with the channel width and length of 34 nm and 31nm respectively, the device has about 3.5 V threshold voltage shift with write voltage of $10\;{\mu}s$, 15 V and erase voltage of 10 ms, -15 V. And retention and endurance characteristics are above 10 years and $10^5$ cycle, respectively. The device with LDD(Lightly Doped Drain) process shows reduction of short channel effect and GIDL(Gate Induced Drain Leakage) current. Moreover we investigate three different types of flash memory arrays.

• Journal of the Semiconductor & Display Technology
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• v.18 no.4
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• pp.134-137
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• 2019

In this paper, the data retention characteristics were analyzed to find out the thickness effect on the trap energy distribution of silicon nitride in the silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices. The nitride films were prepared by low pressure chemical vapor deposition (LPCVD). The flat band voltage shift in the programmed device was measured at the elevated temperatures to observe the thermal excitation of electrons from the nitride traps in the retention mode. The trap energy distribution was extracted using the charge decay rates and the experimental results show that the portion of the shallow interface trap in the total nitride trap amount including interface and bulk trap increases as the nitride thickness decreases.