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http://dx.doi.org/10.4313/JKEM.2012.25.6.409

A Study on a Substrate-bias Assisted 2-step Pulse Programming for Realizing 4-bit SONOS Charge Trapping Flash Memory  

Kim, Byung-Cheul (Department of Electronic Engineering, Gyeongnam National University of Science and Technology(GnTECH))
Kang, Chang-Soo (Department of Electronic Engineering, Yuhan College)
Lee, Hyun-Yong (School of Applied Chemical Engineering, Chonnam National University)
Kim, Joo-Yeon (School of Electricity & Electronics, Ulsan College)
Publication Information
Journal of the Korean Institute of Electrical and Electronic Material Engineers / v.25, no.6, 2012 , pp. 409-413 More about this Journal
Abstract
In this study, a substrate-bias assisted 2-step pulse programming method is proposed for realizing 4-bit/1-cell operation of the SONOS memory. The programming voltage and time are considerably reduced by this programming method than a gate-bias assisted 2-step pulse programming method and CHEI method. It is confirmed that the difference of 4-states in the threshold voltage is maintained to more than 0.5 V at least for 10-year for the multi-level characteristics.
Keywords
4-bit SONOS memory; 2-step pulse programming; Substrate-bias assisted hot electron; Multi-bit; Multi-level;
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