[KSCI] Korea Science Citation Index Service

http://dx.doi.org/10.4313/TEEM.2006.7.4.180

Realization of Two-bit Operation by Bulk-biased Programming Technique in SONOS NOR Array with Common Source Lines

An, Ho-Myoung (Department of Electronic Materials Enginering, Kwangwoon University)
Seo, Kwang-Yell (Department of Electronic Materials Enginering, Kwangwoon University)
Kim, Joo-Yeon (School of Electrical Engineering, Ulsan College)
Kim, Byung-Cheul (Department of Electronic Engineering, Jinju National University)

Publication Information

Transactions on Electrical and Electronic Materials / v.7, no.4, 2006 , pp. 180-183 More about this Journal

Abstract

We report for the first time two-bit operational characteristics of a high-density NOR-type polysilicon-oxide-nitride-oxide-silicon (SONOS) array with common source line (CSL). An undesired disturbance, especially drain disturbance, in the NOR array with CSL comes from the two-bit-per-cell operation. To solve this problem, we propose an efficient bulk-biased programming technique. In this technique, a bulk bias is additionally applied to the substrate of memory cell for decreasing the electric field between nitride layer and drain region. The proposed programming technique shows free of drain disturbance characteristics. As a result, we have accomplished reliable two-bit SONOS array by employing the proposed programming technique.

Keywords

SONOS NOR array; Two-bit operation; Disturbance; Common source lines; Bulk-biased programming technique;

Citations & Related Records

Reference

1	M. H. White, D. A. Adams, and J. Bu, 'On the go with SONOS', Circuits & Devices, p. 22, 2000 DOI
2	S. Minami and Y. Kamigaki, 'A novel MONOS nonvolatile memory device ensuring 10-year data retention after $10^{7}$ erase/write cycles', IEEE Trans. Electron Devices, Vol. 40, No. 11, p. 2011, 1993 DOI ScienceOn
3	M. H. White, Y. Yang, A. Purwar, and M. L. French, 'A low voltage SONOS nonvolatile semiconductor memory technology', IEEE Trans. Comp. Packag. Manufact. Technol. A, Vol. 20, No.2, p. 190, 1997 DOI ScienceOn
4	I. Bloom, P. Pavan, and B. Eitan, ' $NROM^{TM}$ - a new non-volatile memory technology: from device to products', Microelectronic Engineering, Vol. 59, p. 213, 2001 DOI ScienceOn
5	B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, and D. Finzi, 'Can NROM, a 2-bit, trapping storage NVM cell, give a real challenge to floating gate cells?', Proceedings of the International Conference on Solid State Devices and Materials, p. 522, 1999
6	B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, and D. Finzi, 'NROM: a novel localized trapping, 2bit nonvolatile memory cell', IEEE Electron Dev. Lett., Vol. 21, No. 11, p. 543, 2000 DOI ScienceOn