• Korean Journal of Materials Research
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• v.14 no.6
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• pp.413-419
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• 2004

Recently, Silicon On Insulator (SOI) devices emerged to achieve better device characteristics such as higher operation speed, lower power consumption and latch-up immunity. Nevertheless, there are many detrimental defects in SOI wafers such as hydrofluoric-acid (HF)-defects, pinhole, islands, threading dislocations (TD), pyramid stacking faults (PSF), and surface roughness originating from quality of buried oxide film layer. Although the number of defects in SOI wafers has been greatly reduced over the past decade, the turn over of high-speed microprocessors using SOI wafers has been delayed because of unknown defects in SOI wafers. A new characterization method is proposed to investigate the crystalline quality, the buried oxide integrity and some electrical parameters of bonded SOI wafers. In this study, major surface defects in bonded SOI are reviewed using HF dipping, Secco etching, Cu-decoration followed by focused ion beam (FIB) and transmission electron microscope (TEM).

• Korean Journal of Metals and Materials
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• v.46 no.1
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• pp.39-43
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• 2008

PSII (Plasma Source Ion Implantation) using high density pulsed ICP source was employed to implant oxygen ions in Si wafer. The PSII technique can achieve a nominal oxygen dose of $3 {\times}10^{17}atoms/cm^2$ in implantation time of about 20min. In order to prevent oxidation of SOI layer during high temperature annealing, the wafer was capped with $2,000{\AA}$ $Si_3N_4 $ by PECVD. Cross-sectional TEM showed that continuous $500{\AA}$ thick buried oxide layer was formed with $300{\AA}$ thick top silicon layer in the sample. This study showed the possibility of SOI fabrication using the plasma source ion implantation with pulsed ICP source.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.11-12
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• 2007

The electrical characteristics of strained-SOI wafer were evaluated by using pseudo-MOSFET. The electrical characteristics of sSOI pseudo-MOSFET were superior to conventional SOI device. Moreover, the electrical characteristics were enhanced by forming gas anneal due to reduction of back interface trap density between substrate and buried oxide.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.3-4
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• 2005

The Pseudo-MOSFET measurements technique has been used for the electrical characterization of the nano SOL Silicon islands for the Pseudo-MOS measurements were fabricated by selective etching of surface silicon film with dry or wet etching to examine the effects of the etching process on the device properties. The characteristics of the Pseudo-MOS was not changed greatly in the case of thick SOI film which was 205 nm. However the characteristics of the device was dependent on etching process in the case of less than 100 nm thick SOI film. The sub 100nm SOI was obtained by thinning the silicon film of standard thick SOI. The thickness of SOI film was varied from 88 nm to 44 nm by chemical etching. The etching process effects on the properties of pseudo-MOSFET characteristics, such as mobility, turn-on voltage, and drain current transient. The etching process dependency is greater in the thinner SOI and related to original SOI wafer quality.

• Proceedings of the Materials Research Society of Korea Conference
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• 2005.05a
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• pp.53-53
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• 2005

• Electronics and Telecommunications Trends
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• v.5 no.1
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• pp.55-70
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• 1990

SIMOX SOI is known to be one of the most useful technologies for fabrications of new generation ULSI devices. This paper describes the current status of SIMOX SOI technology for ULSI applications. The SIMOX wafer is vertically composed of buried oxide layer and silicon epitaxial layer on top of the silicon substrate. The buried oxide layer is used for the vertical isolation of devices The oxide layer is formed by high energy ion implantation of high dose oxygen into the silicon wafer, followed by high temperature annealing. SIMOX-based CMOS fabrication is transparent to the conventional IC processing steps without well formation. Furthermore, thin film CMOX/SIMOX can overcome the technological limitations which encountered in submicron bulk-based CMOS devices, i.e., soft-error rate, subthreshold slope, threshold voltage roll-off, and hot electron degradation can be improved. SIMOX-based bipolar devices are expected to have high density which comparable to the CMOX circuits. Radiation hardness properties of SIMOX SOI extend its application fields to space and military devices, since military ICs should be operational in radiation-hardened and harsh environments. The cost of SIMOX wafer preparation is high at present, but it is expected to reduce as volume increases. Recent studies about SIMOX SOI technology have demonstrated that the performance of the SIMOX-based submicron devices is superior to the circuits using the bulk silicon.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.5
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• pp.365-371
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• 2003

We prepared silicon on insulator(SOI) wafer pairs of Si/1800${\AA}$ -SiO$_2$ ∥ 1800${\AA}$ -SiO$_2$/Si using water direct bonding method. Wafer pairs bonded at room-temperature were annealed by a normal furnace system or a fast linear annealing(FLA) equipment, and the micro-structure of bonding interfaces for each annealing method was investigated. Upper wafer of bonded pairs was polished to be 50 $\mu\textrm{m}$ by chemical mechanical polishing(CMP) process to confirm the real application. Defects and bonding area of bonded water pairs were observed by optical images. Electrical and mechanical properties were characterized by measuring leakage current for sweeping to 120 V, and by observing the change of wafer curvature with annealing process, respectively. FLA process was superior to normal furnace process in aspects of bonding area, I-V property, and stress generation.

• Proceedings of the KIEE Conference
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• 2002.07c
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• pp.2023-2025
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• 2002

We have fabricated a novel vertical trench-Hall device sensitive to the magnetic field parallel to the sensor chip surface. The vertical trench-Hall device is built on SOI wafer which is produced by silicon direct bonding technology using bulk micromachining, where buried $SiO_2$ layer and surround trench define active device volume. Sensitivity up to 350 V/AT is measured.

• Journal of Sensor Science and Technology
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• v.11 no.1
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• pp.54-59
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• 2002

This paper describes a new process technique for batch process of SOI(Si-on-Insulator) structures with buried cavities for MEMS(Micro Electro Mechanical System) applications by SDB(Si-wafer Direct Bonding) technology and electrochemical etch-stop. A low-cost electrochemical etch-stop method is used to control accurately the thickness of SOI. The cavities were made on the upper handling wafer by Si anisotropic etching. Two wafers are bonded with an intermediate insulating oxide layer. After high-temperature annealing($1000^{\circ}C$, 60 min), the SDB SOI structure with buried cavities was thinned by electrochemical etch-stop. The surface of the fabricated SDB SOI structure have more roughness that of lapping and polishing by mechanical method. This SDB SOI structure with buried cavities will provide a powerful and versatile substrate for novel microsensors arid microactuators.

• Journal of the Korean Vacuum Society
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• v.17 no.2
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• pp.156-159
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• 2008

The electrical characteristic of SiGe-on-SOI (SGOI) wafer with different Ge concentration were evaluated by pseudo-MOSFET. Epitaxial SiGe layers was grown directly on top of SOI with Ge concentrations of 16.2, 29.7, 34.3 and 56.5 at.%. As Ge concentration increased, leakage current increased and threshold voltage shifted from 3 V to 7 V in nMOSFET, from -7 V to -6 V in pMOSFET. The interface states between buried oxide and top of Si was significantly increased by the rapid thermal annealing (RTA) process, and so the electrical characteristic of SGOI wafer degraded. On the other hand, additional post RTA　annealing (PRA) showed that it was effective in decreasing the interface states generated by RTA processes and the electrical characteristic of SGOI wafer enhanced higher than initial state.