• The Journal of the Korea Contents Association
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• v.5 no.1
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• pp.229-236
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• 2005

Testing time and power consumption during testing System-On-a-Chip (SOC) are becoming increasingly important as the IP core increases in a SOC. We present a new algorithm to reduce the scan-in power and test data volume using the modified scan latch reordering. We apply scan latch reordering technique for minimizing the hamming distance in scan vectors. Also, during scan latch reordering, the don't care inputs in scan vectors are assigned for low power and high compression. Experimental results for ISCAS 89 benchmark circuits show that reduced test data and low power scan testing can be achieved in all cases.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.12
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• pp.1045-1054
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• 2002

We present a new low power scan testing and test data compression mothod lot System-On-a-Chip (SOC). The don't cares in unspecified scan vectors are mapped to binary values for low Power and encoded by adaptive encoding method for higher compression. Also, the scan-in direction of scan vectors is determined for low power. Experimental results for full - scanned versions of ISCAS 89 benchmark circuits show that the proposed method has both low power and higher compression.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.293-296
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• 2012

SOC test methodology in ultra deep submicron (UDSM) technology with reasonable test time and cost has begun to satisfy high quality and reliability of the product. A novel hierarchical test architecture using IEEE standard 1149.1, 1149.7 and 1500 compliant facilities is proposed for the purpose of supporting flexible test environment to ensure SOC test methodology. Each embedded core in a system-on- a-chip (SOC) is controlled by test access ports (TAP) and TAP controller of IEEE standard 1149.1 as well as tested using IEEE standard 1500. An SOC device including TAPed cores is hierarchically organized by IEEE standard 1149.7 in wafer and chip level. As a result, it is possible to select/deselect all cores embedded in an SOC flexibly and reduce test cost dramatically using star scan topology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.3
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• pp.65-70
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• 2004

The SOC(System on Chip) testing has required the core re-use methodology and the efficiency of test method because of increase of its cost. The goal of SOC testing is to minimize the testing time, area overhead, and power consumption during testing. Prior research has concentrated on only one aspect of the test core wrapper design problem at a test time. Our research is concentrated on optimization of test time and area overhead for the core test wrapper, which is one of the important elements for SOC test architecture. In this paper, we propose an efficient wrapper design algorithm that improves on earlier approaches by also reducing the TAM(Test Access Mechanism) width required to achieve these lower testing times.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.10a
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• pp.212-215
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• 2005

The needs of larger screen in mobile device would be increased as the time of ubiquitous and convergence is coming. And, the type of mobile device has been evolved from bar, slide to row. Recently, the study on the multi-display screen which has seamless gap between two display panel has been published, and moreover the System On Chip(SOC) design strategy of core chip has been the most promising Field-Programmable Gate Array(FPGA) technology in the display system. Therefore, in this paper, we proposed the design technique of SOC and evaluated the effectiveness with Very high speed Hardware Description Language(VHDL) Intellectual Property (IP) for the operation of multi display device driver. Also, This IP design would be to allow any kind of user interface in control system.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.349-352
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• 2001

As microprocessor and SOC (System On a Chip) performance moves into the GHz speed, the high-speed asynchronous design is becoming challenge due to the disadvantageous power and speed aspects in synchronous designs. The next generation on-chip systems will consist of multiple independently synchronous modules and asynchronous modules for higher performance, so the interface module for data transfer between multiple clocked IPs is designed with Xilinx FPGA and simulated with RISC microprocessor.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.892-895
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• 2011

Power consumption during testing System-On-Chip (SOC) are becoming increasingly important as the IP core increases in SOC. We present a new algorithm to reduce the scan-in power using the modified scan latch reordering and clock gating. We apply scan latch reordering technique for minimizing the hamming distance in scan vectors. Also, during scan latch reordering, the don't care inputs in scan vectors are assigned for low power. Also, we apply the clock gated scan cells. Experimental results for ISCAS 89 benchmark circuits show that reduced low power scan testing can be achieved in all cases.

• Journal of Software Assessment and Valuation
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• v.15 no.1
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• pp.55-62
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• 2019

The needs for small size and low power consumption of information devices is being implemented with SOC technology that implements the program on a single chip in Internet of Thing. Copyright disputes due to piracy are increasing in semiconductor chips as well, arising from disputes in the chip implementation of the design house and chip implementation by the illegal use of the source code. However, since the final chip implementation is made in the design house, it is difficult to protect the copyright. In this paper, we deal with the analysis method for extracting similarity and the criteria for setting similarity judgment in the dispute of source code written in HDL language. Especially, the chip which is manufactured based on the same specification will be divided into the same configuration and the code type.

• The Magazine of the IEIE
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• v.29 no.1
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• pp.66-72
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• 2002

VLSI 기술의 발전은 보다 많은 양의 로직을 단일 칩에 집적 가능하게 했고, 이는 System-on-a-chip 시대의 도래를 가능하게 했다. System-on-a-chip을 가능하게 하기 위해서는 많은 종류의 IP (Intellectual Property)가 필요하고, 공정 변환을 쉽게 하기 위해서는 합성이 가능한 RTL 설계가 절실히 요구된다. 본 논문은 이러한 요구에 부응하기 위해서 hard macro 형태의 기존의 IP로 부터 합성 가능한 IP를 자동 생성해 주는 ART(Automatic RTL Translation)로 명명된 기법에 관한 것이다. 제안된 ART 기법을 이용하여 80C52 호환의 8-bit MCU(Micro-controller Unit)의 합성 가능한 RTL model을 자동 생성하였고, 개발된 Soft IP를 이용하여 TCP/IP 전용 MCU를 표함해서 다양한 제품들을 개발하였다.

• IT SoC Magazine
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• s.16
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• pp.10-11
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• 2006

정보통신부가 주최하고 정보통신연구진흥원, IT-SoC협회, 한국전자통신연구원이 주관하는 ‘IT-SoC Fair 2006’이 지난 11월 1일~2일 양일간 COEX 인도양홀에서 개최되었다. 이 행사는 Fabless 반도체업체들이 중심이 되는 SoC(System on Chip)/IP(Silicon Intellectual Property)전문 전시회로 IT 핵심부품산업을 진흥하고자 하는 취지로 매년 개최되는 행사이다.