JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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Novel Hierarchical Test Architecture for SOC Test Methodology Using IEEE Test Standards

  • Han, Dong-Kwan (Dept. of Electrical & Electronic Engineering, Yonsei University) ;
  • Lee, Yong (Dept. of Electrical & Electronic Engineering, Yonsei University) ;
  • Kang, Sung-Ho (Dept. of Electrical & Electronic Engineering, Yonsei University)
  • Received : 2011.11.21
  • Published : 2012.09.30
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Abstract

SOC test methodology in ultra deep submicron (UDSM) technology with reasonable test time and cost has begun to satisfy high quality and reliability of the product. A novel hierarchical test architecture using IEEE standard 1149.1, 1149.7 and 1500 compliant facilities is proposed for the purpose of supporting flexible test environment to ensure SOC test methodology. Each embedded core in a system-on- a-chip (SOC) is controlled by test access ports (TAP) and TAP controller of IEEE standard 1149.1 as well as tested using IEEE standard 1500. An SOC device including TAPed cores is hierarchically organized by IEEE standard 1149.7 in wafer and chip level. As a result, it is possible to select/deselect all cores embedded in an SOC flexibly and reduce test cost dramatically using star scan topology.

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References

  1. Sunghoon Chun et al., "A New Scan Chain Fault Simulation for Scan Chain Diagnosis", Journal of Semiconductor Technology and Science, vol. 7, 2007.
  2. J.-F. Li et al., "A hierarchical test methodology for systems on chip," Micro, IEEE, vol. 22, 2002.
  3. IEEE Computer Society Test Technology Technical Committee, "IEEE Standard Test Access Port and Boundary-Scan Architecture," January 1990.
  4. IEEE Computer Society, "IEEE Standard Testability Method for Embedded Core-Based Integrated Circuits", Aug. 2005.
  5. IEEE Computer Society, "IEEE Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture", Feb. 2010.

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