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An Efficient Wrapper Design for SOC Testing  

Choi, Sun-Hwa (Department of Computing, Graduate School, Soongsil University)
Kim, Moon-Joon (Department of Computing, Graduate School, Soongsil University)
Chang, Hoon (School of Computing, Soongsil University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.41, no.3, 2004 , pp. 65-70 More about this Journal
Abstract
The SOC(System on Chip) testing has required the core re-use methodology and the efficiency of test method because of increase of its cost. The goal of SOC testing is to minimize the testing time, area overhead, and power consumption during testing. Prior research has concentrated on only one aspect of the test core wrapper design problem at a test time. Our research is concentrated on optimization of test time and area overhead for the core test wrapper, which is one of the important elements for SOC test architecture. In this paper, we propose an efficient wrapper design algorithm that improves on earlier approaches by also reducing the TAM(Test Access Mechanism) width required to achieve these lower testing times.
Keywords
SOC testing; Wrapper; LPT; FFD;
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