• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.6
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• pp.8-15
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• 2003

In this paper, the issue of the differential ring oscillator in designing low phase noise is linearity improvement of delay cell's load resistor. A novel differential delay cell that improves on the Maneatis load is proposed. The linearity improvement of load resistor results in lower phase noise in ring oscillator. For comparison of the phase noise characteristics, Ali Hajimiri's phase noise model is used. In order to have a low ISF(impulse sensitivity function), it is important to have a symmetry between rise time and fall time of oscillation waveform. The ISF value of ing oscillator based on the proposed delay cell is lower than that of the existing ring oscillators. Due to this result, the phase noise is improved by 2~3dBc/Hz for the same power dissipation and oscillation frequency.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.7
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• pp.71-81
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• 2014

In this paper, the performance variations of tri-gate FinFET are analyzed for different fin shapes and source/drain epitaxy types using a 3D device simulator(Sentaurus). If the fin shape changes from a rectangular shape to a triangular shape, the threshold voltage increases due to a non-uniform potential distribution, the off-current decreases by 72.23%, and the gate capacitance decreases by 16.01%. In order to analyze the device performance change from the structural change of the source/drain epitaxy, we compared the grown on the fin (grown-on-fin) structure and grown after the fin etch (etched-fin) structure. 3-stage ring oscillator was simulated using Sentaurus mixed-mode, and the energy-delay products are derived for the different fin and source/drain shapes. The FinFET device with triangular-shaped fin with etched-fin source/drain type shows the minimum the ring oscillator delay and energy-delay product.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.606-609
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• 2003

It is known that 1/f noise of MOSFET is generated by superposition of single Random Telelgraph Signal (RTS). In this study, jitter from 1/f noise of MOSFET is analysed with RTS supplied to one of the nodes of the ring oscillator under investigation. Jitter rates are investigated as the number of stage, power supply voltage, and the amplitude of RTS change.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.21-25
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• 1999

In order to remove minority carries of the base region at changing signal in conventional bipolar logic circuit, we made transistor which is composed of NPN transistor shortened buried layer under the Base region, PNP transistor which is merged in base, epi layer and substrate. Also the Ring-Oscillator for measuring transmission time-delay per gate was designed as well. In the result, we get amplitude of logic voltage of 200mV, the minimum of transmission delay-time of 211nS, and the minimum of transmission delay-time per gate of 7.26ns in AC characteristic output of Ring-Oscillator connected Gate.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.298-302
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• 2006

Models for the phase noise and jitter of the ring oscillator with the power supply noise are suggested and verified by simulations. The power supply noise is converted into the phase-noise by the narrow band phase modulation. The phase-noise appears as sideband frequencies apart from the center frequency of the ring oscillator as much as the frequency of the power supply noise. A jitter model describing the linear relation of jitter with the amplitude of the power supply noise is suggested and verified by simulation.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.6
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• pp.741-746
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• 1986

A novel n-p-n bipolar transistor of which emitter is self-aligned with base contact by polyilicon is developed for using in high speed and high packing density LSI circuits. The emitter of this transistor is separated less than 0.4 \ulcorner with base contact by self-aligh technology, and the emitter feature size is less than 3x5 \ulcorner\ulcorner Because the active region of this transistor is not damaged through all the process, it has excellent electric properties. Using the n-p-n transistors by 3.0\ulcorner design rules, a NTL ring oscillator has 380 ps, a CML ring oscillator has 390ps, and a I\ulcorner ring oscillator has 5.6ns of per-gate minimum propagation delay time.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.2
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• pp.212-215
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• 2016

In this paper, a 5.08 GHz Ring Voltage Controlled Oscillator(Ring VCO) was implemented using $0.18{\mu}m$ standard CMOS technology. The proposal Ring VCO is 3-stage structure. This research confirmed that the each stage's different transistor size ratio influence the current change and alter power consumption consequentially. This circuit is formed to control the current thereby adding the Current Mirror and to tune the frequency by supplying control voltage. It has an 65.5 %(1.88~5.45 GHz) tuning range. The measured output power is -0.30 dBm. The phase noise is -87.50 dBc/Hz @1 MHz offset with operating frequency of 5.08 GHz fundamental frequency. The total power consumption of Ring VCO is 31.2 mW with 2.4 V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.45 no.2
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• pp.37-44
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• 2008

This paper presents a 5.8 GHz PLL using high-speed ring oscillator for WLAN. The proposed ring oscillator has been designed using the negative skewed delay scheme and for differential mode operation. Therefore, the oscillator is insensitive to power-supply-injected noise, and it has the merit of low 1/f noise because tail current sources are not used. The output frequency ranges from 5.13 to 7.04 GHz with the control voltage varing from 0 to 1.8 V. The proposed PLL circuits have been designed, simulated, and proved using 0.18 um 1.8 V TSMC CMOS library. At the operation frequency of 5.8 GHz, the locking time is 2.5 us and the simulated power consumption is 59.9 mW.

• Journal of Navigation and Port Research
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• v.28 no.4
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• pp.293-297
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• 2004

In this papers, an S-band oscillator of the low phase noise property using a miniaturized micro-strip hairpin shaped ring resonator is presented The substrate has a dielectric constant $\epsilon_\gamma$＝3.5, a thickness h＝0.508 mm, and loss tangent $tan\delta$＝0.002. A designed and fabricated oscillator shows low phase noise performance of 99. 71 dBc/Hz at 100 KHz offset frequency and of output power 19.584 dBm at center frequency 2.450 GHz. This circuit was fabricated with hybrid technique, but can be fully compatible with the MMIC due to its entirely planar structure.

• Journal of Information Display
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• v.12 no.1
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• pp.1-4
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• 2011

A complementary inverter was fabricated using pentacene and N-N -dioctyl-3,4,9,10-perylene tetracarboxylic diimide-C (PTCDI-C8) for p- and n-type transistors on a poly(ether sulfone) substrate, respectively. The mobilities of the p- and n-type transistors were 0.056 and 0.013 $cm^2$/Vs, respectively. The inverter, which was composed of p- and n-type transistors, showed a gain of 48.6 when $V_{DD}$ = -40V and at the maximum noise margin of $V_{DD}$/2. A ring oscillator was also fabricated by cascading five inverters. The five-stage ring oscillator showed the maximum output frequency of 10 kHz when $V_{DD}$ = -170 V.