Browse > Article
http://dx.doi.org/10.5573/ieie.2014.51.7.071

Performance Analysis of Tri-gate FinFET for Different Fin Shape and Source/Drain Structures  

Choe, SeongSik (College of Information and Communication Engineering, Sungkyunkwan University)
Kwon, Kee-Won (College of Information and Communication Engineering, Sungkyunkwan University)
Kim, SoYoung (College of Information and Communication Engineering, Sungkyunkwan University)
Publication Information
Journal of the Institute of Electronics and Information Engineers / v.51, no.7, 2014 , pp. 71-81 More about this Journal
Abstract
In this paper, the performance variations of tri-gate FinFET are analyzed for different fin shapes and source/drain epitaxy types using a 3D device simulator(Sentaurus). If the fin shape changes from a rectangular shape to a triangular shape, the threshold voltage increases due to a non-uniform potential distribution, the off-current decreases by 72.23%, and the gate capacitance decreases by 16.01%. In order to analyze the device performance change from the structural change of the source/drain epitaxy, we compared the grown on the fin (grown-on-fin) structure and grown after the fin etch (etched-fin) structure. 3-stage ring oscillator was simulated using Sentaurus mixed-mode, and the energy-delay products are derived for the different fin and source/drain shapes. The FinFET device with triangular-shaped fin with etched-fin source/drain type shows the minimum the ring oscillator delay and energy-delay product.
Keywords
FinFET; triangular-shaped fin; rectangular-shaped fin; epitaxy; stress; ring oscillator;
Citations & Related Records
Times Cited By KSCI : 3  (Citation Analysis)
연도 인용수 순위
1 Myung-Dong Ko et al., "Study on a Scaling Length Model for Tapered Tri-Gate FinFET Based on 3-D Simulation and Analytical Analysis", IEEE Trans. Electron Devices, vol. 60, no. 9, pp. 2721-2727, Sept. 2013.   DOI   ScienceOn
2 Kehuey Wu et al., "Performance Advantage and Energy Saving of Triangular-Shaped FinFETs", Proc. International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp. 143-146, 3-5 Sept. 2013.
3 Ohkura, Y. et al., "Analysis of gate currents through high-k dielectrics using a Monte Carlo device simulator", Proc. International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp. 67-70, 3-5 Sept. 2003.
4 Kah-Wee Ang et al., "Strained n-MOSFET with embedded source/drain stressors and strain-transfer structure(STS) for enhanced transistor performance", IEEE Trans. Electron Devices, vol. 55, no. 3, pp. 850-857, Mar. 2008.   DOI   ScienceOn
5 C. R. Manoj et al., "Impact of High-k Gate Dielectrics on the Device and Circuit Performance of Nanoscale FinFETs", IEEE Electron Device Letters, vol. 28, no. 4, pp. 295-297, April 2007.   DOI   ScienceOn
6 Tsung-Yang Liow et al., "N-channel (110)-sidewall strained FinFETs with silicon-carbon source and drain stressors and tensile capping layer", IEEE Electron Device Letters, vol. 28, no. 11, pp. 1014-1017, Nov. 2007.   DOI   ScienceOn
7 Kian-Ming Tan et al., "Strained p-channel FinFETs with extended pi-shaped silicon-germanium source and drain stressors", IEEE Electron Device Letters, vol. 28, no. 10, pp. 905-908, Oct. 2007.   DOI   ScienceOn
8 Synopsys Sentaurus Device User Guide Ver.H-2013.03.
9 M. Garcia Bardon et al., "Layout-induced stress effects in 14nm & 10nm FinFETs and their impact on performance", in Proc. Symp. VLSI Technology, pp. 114-115, Jun. 2013.
10 Elio Consoli et al., "Conditional Push-Pull Pulsed Latches with 726fJ.ps Energy-Delay Product in 65nm CMOS", in Proc. ISSCC, 2012, pp. 482-484.
11 J. M. Rabaey, A. Chandrakasan, B. Nikolic, Digital Integrated Circuits : A Design Perspective, 2nd Edition, Prentice Hall, pp. 226, 2004.
12 The International Technology Roadmap for Semiconductors(ITRS), 2011
13 Jihyun Kim, Aeri Son, Narae Jeong, and Hyungsoon Shin, "2D Quantum Effect Analysis of Nanoscale Double-Gate MOSFET," Journal of The Institute of Electronics Engineers of Korea, vol. 45SD, no. 10, pp. 15-22, Oct. 2008.   과학기술학회마을
14 C. Auth et al., "A 22nm High Performance and Low-Power CMOS Technology Featuring Fully-Depleted Tri-Gate Transistors, Self-Aligned Contacts and High Density MIM Capacitors", Symposium on VLSI Technology, 12-14 June. 2012.
15 K. W. Lee, SeokSoon Noh, NaHyun Kim, KeeWon Kwon, and SoYoung Kim, "Comparative study of analog performance of multiple fin tri-gate FinFETs," International Conference on Electronics, Information and Communication, 2012.
16 Chi Woo Lee, Serena Yun, Chong Gun Yu, and Jong Tae Park, "A study on the device structure optimization of nano-scale MuGFETs," Journal of The Institute of Electronics Engineers of Korea, vol. 43SD, no. 4, pp.23-30, Apr. 2006.   과학기술학회마을
17 SeokSoon Noh, KeeWon Kwon, and SoYoung Kim, "Analysis of Process and Layout Dependent Analog Performance of FinFET Structures using 3D Device Simulator," Journal of The Institute of Electronics Engineers of Korea, vol. 50SD, no. 4, pp. 35-42, Apr. 2013.   과학기술학회마을   DOI   ScienceOn
18 C. H. Jan et al., "A 22nm SoC Platform Technology Featuring 3-D Tri-Gate and High-k/Metal Gate, Optimized for Ultra Low Power, High Performance and High Desity SoC Applications", Electron Device Meeting (IEDM), pp. 3.1.1-3.1.4, 10-13 Dec. 2012.
19 N. Serra et al., "Experimental and physics-based modeling assessment of strain induced mobility enhancement in FinFETs", Electron Deivces Meeting (IEDM), pp. 1-4, 7-9 Dec. 2009.
20 Lori Washington et al., "pMOSFET With 200% Mobility Enhancement Induced by Mutiple Stressors", IEEE Electron Device Letters, vol. 27, no. 6, pp. 511-513, June. 2006.   DOI   ScienceOn
21 W. Yang and J. G. Fossum, "On the feasibility of nanoscale triple gate CMOS transistors," IEEE Trans. Electron Devices, vol. 52, no. 6, pp. 1159-1164, Jun. 2005.   DOI   ScienceOn