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5.8 GHz PLL using High-Speed Ring Oscillator for WLAN  

Kim, Kyung-Mo (Memory Div., Samsung Electronics)
Choi, Jae-Hyung (Dept. of Electronics Engineering, Dongguk University)
Kim, Sam-Dong (Dept. of Electronics Engineering, Dongguk University)
Hwang, In-Seok (Dept. of Electronics Engineering, Dongguk University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SC / v.45, no.2, 2008 , pp. 37-44 More about this Journal
Abstract
This paper presents a 5.8 GHz PLL using high-speed ring oscillator for WLAN. The proposed ring oscillator has been designed using the negative skewed delay scheme and for differential mode operation. Therefore, the oscillator is insensitive to power-supply-injected noise, and it has the merit of low 1/f noise because tail current sources are not used. The output frequency ranges from 5.13 to 7.04 GHz with the control voltage varing from 0 to 1.8 V. The proposed PLL circuits have been designed, simulated, and proved using 0.18 um 1.8 V TSMC CMOS library. At the operation frequency of 5.8 GHz, the locking time is 2.5 us and the simulated power consumption is 59.9 mW.
Keywords
PLL; Ring Oscillator; Negative Skewed Delay Scheme;
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Times Cited By KSCI : 1  (Citation Analysis)
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1 C. Hung, L. Shi, I. Laguado, and K. K. O, "A 25.9GHz Voltage-Controlled Oscillator Fabricatied in a CMOS Process," IEEE Symp. on VLSI Circuits, pp. 100-101, 2000
2 Kuo-Hsing Cheng, Ching-Wen Lai and Yu-Lung Lo, "A CMOS VCO for 1V, 1GHz PLL Applications," 2004 IEEE Asian-Pacific Conference on Advanced System Integrated Circuits, pp. 150-153, Aug. 2004
3 Joonsuk Lee, Beomsup Kim, "A low-noise fast-lock phase-locked loop with adaptive bandwidth control," IEEE Journal of Solid-State Circuits, Vol, 35, issue 8, pp. 1137-1145, Aug. 2000   DOI   ScienceOn
4 M. Tiebout, H. Wohlmuth, an W. Simburger, "A 1 V 51 GHz Fully-Integrated VCO in 0.12 um CMOS," ISSCC Dig. of Tech. Papers, pp. 300-301, 2002
5 Chan-Hong Park, Beomsup Kim, "A low-noise, 900-MHz VCO in 0.6um CMOS," IEEE Journal of Solid-State Circuits, Vol. 34, issue 5, pp. 586-591, May 1999   DOI   ScienceOn
6 이승훈, 김범섭, 송민규, 최중호, CMOS 아날로그/혼성모드 집적시스템 설계, 시그마 프레스, 1999
7 T. K. K. Tsang and M. N. El-Gamal, "A High Fiqure of Merit and Area-Efficient Low-Voltage(0.7-1V) 12GHz CMOS VCO," 2003 IEEE RFIC Symp, Dig., pp. 89-92, Jun. 2003
8 J. H. C. Zhan, J.S. Duster and K. T. Kornegay, "Analysis of Emitter Degenerated LC Oscillators Using Bipolar Technologies," IEEE Symp. Circuits and Systems 2003, pp. 669-672
9 김성하, 김삼동, 황인석, "향상된 부 스큐 고속 VCO를 이용한 초고주파 PLL," 전자공학회 논문지 제 42 권 SC편 제 6 호, pp. 23-36, Nov. 2005   과학기술학회마을
10 In-Chul Hwang, Chulwoo Kim. and Sung-mo Kang, "A CMOS Self-Regulating VCO with low supplys sensitivity," IEEE Journal of Solid-State Circuits, Vol, 39, issue 1, pp. 42-48, Jan. 2004   DOI   ScienceOn
11 Seong-Jun Lee, Beomsup Kim, Kwyro Lee, "A novel high-speed ring oscillator for multiphase clock generation using negative skewed delay scheme," IEEE Journal of Solid-State Circuits, Vol, 33, issue 2, pp. 289-291, Feb. 1997