1 |
Ian A.Young, et al., 'A PLL Clock Generator with 5 to 110MHz of Lock Range for Micro processors,' IEEE JSSC, vol. 27, pp. 1599-1607, November, 1992
DOI
ScienceOn
|
2 |
John G.Maneatis and Mark A. Horowitz, 'Precise Delay Generation Using Coupled Oscillators,' IEEE JSSC, vol. 28, pp. 1273-1282, December, 1993
DOI
ScienceOn
|
3 |
Ali Hajimiri, et al., 'Jitter and Phase Noise in Ring Oscillators,' IEEE JSSC, vol. 34, pp. 790-804, June, 1999
DOI
ScienceOn
|
4 |
Liang Dai and Ramesh Harjani, 'Comparison and Analysis of Phase Noise Ring Oscillators,' IEEE International Symposium on Circuits and Systems, pp. 77-80, May, 2000
DOI
|
5 |
S. I. Gierkink, et al., 'Intrinsic 1/f device noise reduction and its effect on phase noise in CMOS ring oscillators,' IEEE JSSC, vol. 34, pp. 1022-1025, July, 1999
DOI
ScienceOn
|
6 |
B. Kim and P. Gray, 'A 30MHz hybrid analog/digital clock recovery circuit in CMOS,' IEEE JSSC, vol. 25, pp. 1385-1394, December, 1990
DOI
ScienceOn
|
7 |
Thomas H.Lee and Ali Hajimiri, 'Oscillator Phase Noise: A Tutorial,' IEEE JSSC, vol. 35, pp. 326-336, March, 2000
DOI
ScienceOn
|
8 |
A. W. Buchwald, et al., 'A 6-GHz integrated phase-locked loop using AlGaAs/Ga/As heterojunction bipolar transistors,' IEEE JSSC, vol. 27, pp. 1752-1762, December, 1992
DOI
ScienceOn
|
9 |
W. D. Liewellyn, et al., 'A 33Mbi/s data synchronizing phase-locked loop circuit,' in ISSCC Dig. Tech. Papers, pp. 12-13, February, 1988
|