• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.383-386
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• 1988

In MOS integrated circuits, annealing after oxidation process is necessary to improve physical properties of silicon dioxide. With subsequent annealing in inert gases such as nitrogen or argon, and excess silicon bond is allowed time to complete the oxidation and surface charge density is reduced. In this paper, we will present effects of the rapid thermal annealing on silicon dioxide. In order to evaluate characteristics of silicon dioxide, we analyzed C-V curve dependent on annealing time and temperature, and presented variation of fixed oxide charge.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.2
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• pp.83-88
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• 2005

The interface-states between the top silicon layer and buried oxide layer of nano-SOI substrate were developed. Also, the effects of thermal treatment processes on the interface-state distributions were investigated for the first time by using pseudo-MOSFETs. We found that the interface-state distributions were strongly influenced by the thermal treatment processes. The interface-states were generated by the rapid thermal annealing (RTA) process. Increasing the RTA temperature over $800^{\circ}C$, the interface-state density considerably increased. Especially, a peak of interface-states distribution that contributes a hump phenomenon of subthreshold curve in the inversion mode operation of pseudo-MOSFETs was observed at the conduction band side of the energy gap, hut it was not observed in the accumulation mode operation. On the other hand, the increased interface-state density by the RTA process was effectively reduced by the relatively low temperature annealing process in a conventional thermal annealing (CTA) process.

• Journal of the Korean Ceramic Society
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• v.32 no.8
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• pp.881-892
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• 1995

Sol-Gel derived ferroelectric PZT thin films were fabricated on ITO/Glass substrate. Two kinds of rapid thermal annealing methods, R-I (six times of intermediate and final annealing) and R-II (one final annealing after six times of intermediate annealing) were used for preparation of multi-coated PZT thin films. 2500$\AA$-thick PZT thin films were obtained by the R-I and R-II methods and characterized by microstructure and dielectric properties. In case of using R-II, the microstructure was finer than that of R-I and there was no distinguishable difference in dielectric properties of PZT thin films between the R-I and R-II methods. But dielectric properties were enhanced by increasing perovskite phase fraction with increasing annealing temperature. Measured dielectric constant of PZT thin film annealed at 62$0^{\circ}C$ using the R-I method was 256 at 1kHz. Its remanant polarization (Pr) and coercive field (Ec) were 14.4$\mu$C/$\textrm{cm}^2$ and 64kV/cm, respectively.

• Korean Journal of Materials Research
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• v.24 no.9
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• pp.443-450
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• 2014

Amorphous (a-Si) films were epitaxially crystallized on a very thin large-grained poly-Si seed layer by a silicide-enhanced rapid thermal annealing (SERTA) process. The poly-Si seed layer contained a small amount of nickel silicide which can enhance crystallization of the upper layer of the a-Si film at lower temperature. A 5-nm thick poly-Si seed layer was then prepared by the crystallization of an a-Si film using the vapor-induced crystallization process in a $NiCl_2$ environment. After removing surface oxide on the seed layer, a 45-nm thick a-Si film was deposited on the poly-Si seed layer by hot-wire chemical vapor deposition at $200^{\circ}C$. The epitaxial crystallization of the top a-Si layer was performed by the rapid thermal annealing (RTA) process at $730^{\circ}C$ for 5 min in Ar as an ambient atmosphere. Considering the needle-like grains as well as the crystallization temperature of the top layer as produced by the SERTA process, it was thought that the top a-Si layer was epitaxially crystallized with the help of $NiSi_2$ precipitates that originated from the poly-Si seed layer. The crystallinity of the SERTA processed poly-Si thin films was better than the other crystallization process, due to the high-temperature RTA process. The Ni concentration in the poly-Si film fabricated by the SERTA process was reduced to $1{\times}10^{18}cm^{-3}$. The maximum field-effect mobility and substrate swing of the p-channel poly-Si thin-film transistors (TFTs) using the poly-Si film prepared by the SERTA process were $85cm^2/V{\cdot}s$ and 1.23 V/decade at $V_{ds}=-3V$, respectively. The off current was little increased under reverse bias from $1.0{\times}10^{-11}$ A. Our results showed that the SERTA process is a promising technology for high quality poly-Si film, which enables the fabrication of high mobility TFTs. In addition, it is expected that poly-Si TFTs with low leakage current can be fabricated with more precise experiments.

• Electrical & Electronic Materials
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• v.8 no.6
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• pp.737-743
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• 1995

Two step RTD(Rapid Thermal Diffussion) of P into silicon wafer using tungsten halogen lamp was used to fabricated very shallow n$^{+}$p junction. 1st RTD was performed in the temperature range of 800.deg. C for 60 see and the heating rate was in the 50.deg. C/sec. Phosphrous solid source was transfered on the silicon surface. 2nd RTD process was performed in the temperature range 1050.deg. C, 10sec. Using 2 step RTD we can obtain a shallow junction 0.13.mu.m in depth. After RTD, the Ti-silicide process was performed by the two step RTA(Rapid Thermal Annealing) to reduced the electric resistance and to improve the n$^{+}$p junction diode. The titanium thickness was 300.angs.. The condition of lst RTA process was 600.deg. C of 30sec and that of 2nd RTA process was varied in the range 700.deg. C, 750.deg. C, 800.deg. C for 10sec-60sec. After 2 step RTA, sheet resistance was 46.ohm../[]. Ti-silicide n+p junction diode was fabricated and I-V characteristics were measured.red.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.36 no.6
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• pp.576-581
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• 2023

The Ga₂O₃ thin films were deposited using an RF sputtering system and the effect of crystallographic and optical properties under rapid thermal annealing conditions on Ga₂O₃ thin film was evaluated. A rapid thermal annealing method can fabricate a crystalline Ga₂O₃ thin film which is applied to various fields with a low cost and a high efficiency compared with the conventional post-annealing method. In this study, the Ga₂O₃ treated at 900℃ for 1 min showed the beta and gamma phases in XRD measurement. In optical properties, the crystalline Ga₂O₃ represented a high transmittance of more than 80% in the visible region and was calculated with a high optical bandgap energy of 4.58 eV. The beta and gamma phases Ga₂O₃ can be obtained by adjusting the rapid thermal annealing temperatures, and the various properties such as the optical bandgap energy can be controlled. Moreover, it is expected that crystalline Ga₂O₃ can be applied to various devices by controlling not only temperature but process time.

• Journal of the Korean Vacuum Society
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• v.1 no.1
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• pp.168-175
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• 1992

The surface and interface morphology as well as the sheet resistance, and uniformity of TiSiz film are significantly improved and the lateral titanium silicide growth over the oxide spacer is minimized by the use of ion beam mixing and rapid thermal annealing in nitrogen ambient. In addition, TiSiz film formations on TiISi and TiISiOz system were also studied.

• Journal of the Semiconductor & Display Technology
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• v.23 no.1
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• pp.88-91
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• 2024

The europium doped yttrium oxide (Y₂O₃:Eu³⁺) thin film was formed on a Si substrate by the conventional spin-coating process followed by rapid thermal annealing (RTA) treatment. The spinning profiles such as rotation speed, acceleration and holding times were controlled during the spin-coating process for the best condition of the Y₂O₃:Eu³⁺ thin film. The RTA treatment was conducted for several temperature in order to crystallize the spin coated film. The Y₂O₃:Eu³⁺ thin film presented best performance in the conditions of 4000 rpm, 30 s and 10 s of rotation speed, acceleration time and holding time, respectively, at a fixed RTA temperature of 900 ℃.

• Current Photovoltaic Research
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• v.1 no.2
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• pp.82-89
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• 2013

$Cu_2ZnSnS_4$ thin film have been fabricated by rapid thermal annealing of dc-sputtered metal precursor with Cu/ZnSn/Cu stack in sulfur ambient. A CZTS film with a good uniformity was formed at $560^{\circ}C$ in 6 min. $Cu_2SnS_3$ and $Cu_3SnS_4$ secondary phases were present at $540^{\circ}C$ and a trace amount of $Cu_2SnS_3$ secondary phase was present at $560^{\circ}C$. Single-phase large-grained CZTS film with rough surface was formed at $560^{\circ}C$. Solar cell with best efficiency of 4.7% ($V_{oc}=632mV$, $j_{sc}=15.8mA/cm^2$, FF = 47.13%) for an area of $0.44cm^2$ was obtained for the CZTS absorber grown at $560^{\circ}C$ for 6 min. The existence of second phase at lower-temperature annealing and rough surface at higher-temperature annealing caused the degradation of cell performance. Also poor back contact by void formation deteriorated cell performance. The fill factor was below 0.5; it should be increased by minimizing voids at the CZTS/Mo interface. Our results suggest that CZTS absorbers can be grown by rapid thermal annealing of metallic precursors in sulfur ambient for short process times ranging in minutes.

• 대한공업교육학회지
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• v.33 no.1
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• pp.249-264
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• 2008

In this dissertation, shallow $p^+-n$ junctions were formed by ion implantation and dual-step annealing processes and a new simulator is designed to model boron diffusion in silicon. This simulator predicts the boron distribution after ion implantation and annealing. The dopant implantation was performed into the crystalline substrates using $BF_2$ ions. The annealing was performed with a RTA(Rapid Thermal Annealing) and a FA(Furnace Annealing) process. The model which is used in this simulator takes into account nonequilibrium diffusion, reactions of point defects, and defect-dopant pairs considering their charge states, and the dopant inactivation by introducing a boron clustering reaction. FA+RTA annealing sequence exhibited better junction characteristics than RTA+FA thermal cycle from the viewpoint of sheet resistance and the simulator reproduced experimental data successfully. Therefore, proposed diffusion simulator and FA+RTA annealing method was able to applied to shallow junction formation for thermal budget. process.