• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2010년도 추계학술대회 논문집
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• pp.593-594
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• 2010

• 대한전자공학회논문지
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• 제27권9호
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• pp.1409-1418
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• 1990

Characteristics of NMOS transistors with phosphorus source/drain junctions formed by two-step rapid thermal diffusion (RTD) process using a solid diffusion source have been investigated. Phosphorus profiles after RTD were measured by SIMS analysis. In the case of 1100\ulcorner, 10sec RTD of, P, the specific contact resistance of n+ Si-Al was 2.4x10**-7 \ulcorner-cm\ulcorner which is 1/5 of the As junction The comparison fo P junction devices formed by RTD and conventional As junction devices shows that both short channel effect and hot carrier effect of P junction devices are smaller than those of As junction devices when the devices have same junction depths. P junction device had maximum of 0.4 times lower Isub/Id than As junction device. Characteristics of P junction formed by several different RTD conditions have been compared and 1000\ulcorner RTD sample had the smaller hot carrier generation. Also, it has been shown that the hot carrier generation can be futher reduced by forming the P junctions by 3-step RTD which has RTO-driven-in process additionally.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권1호
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• pp.16-21
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• 2006

A simple doping method to fabricate a very thin channel body of the p-type FinFETs with a 20 nm gate length by solid-phase-diffusion (SPD) process was developed. Using the poly-boron-films (PBF) as a novel diffusion source of boron and the rapid thermal annealing (RTA), the p-type sourcedrain extensions of the FinFET devices with a threedimensional structure were doped. The junction properties of boron doped regions were investigated by using the $p^+-n$ junction diodes which showed excellent electrical characteristics. Single channel and multi-channel p-type FinFET devices with a gate length of 20-100 nm was fabricated by boron diffusion process using PBF and revealed superior device scalability.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
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• pp.133-134
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• 2006

A simple doping method to fabricate a very thin channel body of the n-type fin field-effect-transistor (FinFET) with a 20 nm gate length by solid-phase-diffusion (SPD) process is presented. Using As-doped spin-on-glass as a diffusion source of arsenic and the rapid thermal annealing, the n-type source-drain extensions with a three-dimensional structure of the FinFET devices were doped. The junction properties of arsenic doped regions were investigated by using the $n^+$-p junction diodes which showed excellent electrical characteristics. Single channel and multi-channel n-type FinFET devices with a gate length of 20-100 nm was fabricated by As-SPD and revealed superior device scalability.

• 한국전기전자재료학회논문지
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• 제20권5호
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• pp.394-398
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• 2007

A simple doping method to fabricate a very thin channel body of the nano-scaled n-type fin field-effect-transistor (FinFET) by arsenic solid-Phase-diffusion (SPD) process is presented. Using the As-doped spin-on-glass films and the rapid thermal annealing for shallow junction, the n-type source-drain extensions with a three-dimensional structure of the FinFET devices were doped. The junction properties of arsenic doped regions were investigated by using the $n^+$-p junction diodes which showed excellent electrical characteristics. The n-type FinFET devices with a gate length of 20-100 nm were fabricated by As-SPD and revealed superior device scalability.

• Applied Science and Convergence Technology
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• 제26권6호
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• pp.208-213
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• 2017

Flexible opto-electronic devices are developed on the insulating layer deposited stainless steel (STS) substrates. The silicon dioxide ($SiO_2$) material as the diffusion barrier of Fe and Cr atoms in addition to the electrical insulation between the electronic device and STS is processed using the plasma enhanced chemical vapor deposition method. Noble silver (Ag) films of approximately 100 nm thickness have been formed on $SiO_2$ deposited STS substrates by E-beam evaporation technique. The films then were annealed at $650^{\circ}C$ for 20 min using the rapid thermal annealing (RTA) technique. It was investigated the variation of the surface morphology due to the interaction between Ag films and $SiO_2$ layers after the RTA treatment. The results showed the movement of Si atoms in silver film from $SiO_2$. In addition, the structural investigation of Ag annealed at $650^{\circ}C$ indicated that the Ag film has the material property of p-type semiconductor and the bandgap of approximately 1 eV. Also, the films annealed at $650^{\circ}C$ showed reflection with sinusoidal oscillations due to optical interference of multiple reflections originated from films and substrate surfaces. Such changes can be attributed to both formation of $SiO_2$ on Ag film surface and agglomeration of silver film between particles due to annealing.

• 한국결정성장학회지
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• 제6권3호
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• pp.424-430
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• 1996

태양전지의 공정중 고온공정을 줄여줌으로서 최종 태양전지의 가격을 저가화할 수가 있다. 이 논문은 점액 상태의 인을 희석시켜서 접촉 홈에 확산공정을 마친 후, 그 기본 특성을 조사하였다. 점액상태점의 희석도와 스핀속도가 산화막의 두께에 영향을 미치는 것이 확인되었다. 희석도가 높을수록 산화막은 두꺼워지고 균일도는 낮아졌다. 희석도 60%의 인이 홈에서의 균일도와 깊이를 고려할 때 가장 적당한 것으로 사료된다.

• 융합정보논문지
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• 제10권8호
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• pp.137-143
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• 2020

SiO2 증착된 금속 호일 기판에 형성된 은 금속 박막의 급속 열처리에 대한 물리적 및 화학적 특성 영향을 조사하였다. 은 박막을 150도에서 550도까지 온도를 변화시키며, 각 온도에서 20분 동안 급속 열처리를 진행하였다. 550도에서 표면 거칠기와 저항이 급격하게 증가하는 현상을 발견하였다. 따라서 550도의 열처리 온도 샘플에 대해 조성 분석 기법을 사용하였고, 은 필름 표면에 산소 (O) 및 실리콘 (Si) 원자가 존재함을 확인하였다. 박막의 광학적 특성인, 전체 반사율은 온도가 증가함에 따라 감소하였으며, 특히 550도에서 공정을 진행한 박막은 박막 및 기판 표면으로부터의 다중 반사에 의한 광학적 간섭으로 인해 정현파 특성을 나타냄을 확인하였다. 이러한 현상은 급속 열처리 동안 SiO2 층으로부터 Si 원자의 외부 확산에 기인한 것이다. 본 연구 결과는 다양한 플렉서블 광전자소자의 기판으로 사용할 수 있는 가능성을 제공한다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2015년도 제49회 하계 정기학술대회 초록집
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• pp.259-259
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• 2015

Single crystalline indium-tin-oxide (ITO) nanowires (NWs) were grown by sputtering method. A thin Ni film of 5 nm was deposited before ITO sputtering. Thermal treatment forms Ni nanoparticles, which act as templates to diffuse Ni into the sputtered ITO layer to grow single crystalline ITO NWs. This Ni diffusion through an ITO NW was investigated by transmission electron microscope to observe the Ni-tip sitting on a single crystalline ITO NW. Meanwhile, a single crystalline ITO structure was found at bottom and body part of a single ITO NW without remaining of Ni atoms. This indicates the Ni atoms diffuse through the oxygen vacancies of ITO structure. Rapid thermal process (RTP) applied to generate an initial stage of a formation of Ni nanoparticles with variation in time periods to demonstrate the existence of an optimum condition to initiate ITO NW growth. Modulation in ITO sputtering condition was applied to verify the ITO NW growth or the ITO film growth. The Ni-assisted grown ITO layer has an improved electrical conductivity while maintaining a similar transmittance value to that of a single ITO layer. Electrically conductive and optically transparent nanowire-coated surface morphology would provide a great opportunity for various photoelectric devices.

• 한국재료학회지
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• 제16권9호
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• pp.564-570
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• 2006

Silicides have been required to be below 40 nm-thick and to have low contact resistance without agglomeration at high silicidation temperature. We fabricated composite silicide layers on the wafers from Ni(20 nm)/Co(20 nm)/poly-Si(70 nm) structure by rapid thermal annealing of $700{\sim}1100^{\circ}C$ for 40 seconds. The sheet resistance, surface composition, cross-sectional microstructure, and surface roughness were investigated by a four point probe, a X-ray diffractometer, an Auger electron spectroscopy, a field emission scanning electron microscope, and a scanning probe microscope, respectively. The sheet resistance increased abruptly while thickness decreased as silicidation temperature increased. We propose that the fast metal diffusion along the silicon grain boundary lead to the poly silicon mixing and inversion. Our results imply that we may consider the serious thermal instability in designing and process for the sub-0.1 um CMOS devices.