• Proceedings of the Korean Society of Precision Engineering Conference
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• 2010.11a
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• pp.593-594
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• 2010

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.9
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• pp.1409-1418
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• 1990

Characteristics of NMOS transistors with phosphorus source/drain junctions formed by two-step rapid thermal diffusion (RTD) process using a solid diffusion source have been investigated. Phosphorus profiles after RTD were measured by SIMS analysis. In the case of 1100\ulcorner, 10sec RTD of, P, the specific contact resistance of n+ Si-Al was 2.4x10**-7 \ulcorner-cm\ulcorner which is 1/5 of the As junction The comparison fo P junction devices formed by RTD and conventional As junction devices shows that both short channel effect and hot carrier effect of P junction devices are smaller than those of As junction devices when the devices have same junction depths. P junction device had maximum of 0.4 times lower Isub/Id than As junction device. Characteristics of P junction formed by several different RTD conditions have been compared and 1000\ulcorner RTD sample had the smaller hot carrier generation. Also, it has been shown that the hot carrier generation can be futher reduced by forming the P junctions by 3-step RTD which has RTO-driven-in process additionally.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.1
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• pp.16-21
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• 2006

A simple doping method to fabricate a very thin channel body of the p-type FinFETs with a 20 nm gate length by solid-phase-diffusion (SPD) process was developed. Using the poly-boron-films (PBF) as a novel diffusion source of boron and the rapid thermal annealing (RTA), the p-type sourcedrain extensions of the FinFET devices with a threedimensional structure were doped. The junction properties of boron doped regions were investigated by using the $p^+-n$ junction diodes which showed excellent electrical characteristics. Single channel and multi-channel p-type FinFET devices with a gate length of 20-100 nm was fabricated by boron diffusion process using PBF and revealed superior device scalability.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.133-134
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• 2006

A simple doping method to fabricate a very thin channel body of the n-type fin field-effect-transistor (FinFET) with a 20 nm gate length by solid-phase-diffusion (SPD) process is presented. Using As-doped spin-on-glass as a diffusion source of arsenic and the rapid thermal annealing, the n-type source-drain extensions with a three-dimensional structure of the FinFET devices were doped. The junction properties of arsenic doped regions were investigated by using the $n^+$-p junction diodes which showed excellent electrical characteristics. Single channel and multi-channel n-type FinFET devices with a gate length of 20-100 nm was fabricated by As-SPD and revealed superior device scalability.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.5
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• pp.394-398
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• 2007

A simple doping method to fabricate a very thin channel body of the nano-scaled n-type fin field-effect-transistor (FinFET) by arsenic solid-Phase-diffusion (SPD) process is presented. Using the As-doped spin-on-glass films and the rapid thermal annealing for shallow junction, the n-type source-drain extensions with a three-dimensional structure of the FinFET devices were doped. The junction properties of arsenic doped regions were investigated by using the $n^+$-p junction diodes which showed excellent electrical characteristics. The n-type FinFET devices with a gate length of 20-100 nm were fabricated by As-SPD and revealed superior device scalability.

• Applied Science and Convergence Technology
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• v.26 no.6
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• pp.208-213
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• 2017

Flexible opto-electronic devices are developed on the insulating layer deposited stainless steel (STS) substrates. The silicon dioxide ($SiO_2$) material as the diffusion barrier of Fe and Cr atoms in addition to the electrical insulation between the electronic device and STS is processed using the plasma enhanced chemical vapor deposition method. Noble silver (Ag) films of approximately 100 nm thickness have been formed on $SiO_2$ deposited STS substrates by E-beam evaporation technique. The films then were annealed at $650^{\circ}C$ for 20 min using the rapid thermal annealing (RTA) technique. It was investigated the variation of the surface morphology due to the interaction between Ag films and $SiO_2$ layers after the RTA treatment. The results showed the movement of Si atoms in silver film from $SiO_2$. In addition, the structural investigation of Ag annealed at $650^{\circ}C$ indicated that the Ag film has the material property of p-type semiconductor and the bandgap of approximately 1 eV. Also, the films annealed at $650^{\circ}C$ showed reflection with sinusoidal oscillations due to optical interference of multiple reflections originated from films and substrate surfaces. Such changes can be attributed to both formation of $SiO_2$ on Ag film surface and agglomeration of silver film between particles due to annealing.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.6 no.3
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• pp.424-430
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• 1996

The present processing sequence for solar cells is very elaborate and ads to the cost of the fabricated cells. This processing cost, which accounts for about 30% of the total cost, can be reduced if the many high temperature sequences can be reduced without significantly reducing the cells energy conversion efficiency. By using the spin-on glasses (SOG) in conjunction with the conventional tube furnace (CTF) or rapid thermal annealer (RTA), the many high temperature process can be reduced to only one. In order to achieve efficiencies similar to the standard high temperature sequences using the solid or liquid sources, some basic characterization of the groove diffusion is necessary to ascertain the its suitability. This paper describes the work done in diffusing the buried contact grooves using the phosphorus SOG.

• Journal of Convergence for Information Technology
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• v.10 no.8
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• pp.137-143
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• 2020

This study examined the effects of rapid thermal annealing (RTA) on the physical and chemical characteristics of thin silver (Ag) layers on SiO2 coated metal foils. Ag layers were annealed at various temperatures of the range between 150 ℃ and 550 ℃ for 20 min. The surface roughness and resistivity are increased at the annealing temperatures of 550 ℃. We also found that oxygen (O) and silicon (Si) atoms exist at the Ag film surface by using compositional analysis in the annealing temperatures of 550 ℃. The total reflectance is decreased with increasing temperature. These phenomena are due to an out-diffusion of Si atoms from SiO2 layers during the RTA annealing. The results offer the possibility of using it as a substrate for various flexible optoelectronic devices.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.259-259
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• 2015

Single crystalline indium-tin-oxide (ITO) nanowires (NWs) were grown by sputtering method. A thin Ni film of 5 nm was deposited before ITO sputtering. Thermal treatment forms Ni nanoparticles, which act as templates to diffuse Ni into the sputtered ITO layer to grow single crystalline ITO NWs. This Ni diffusion through an ITO NW was investigated by transmission electron microscope to observe the Ni-tip sitting on a single crystalline ITO NW. Meanwhile, a single crystalline ITO structure was found at bottom and body part of a single ITO NW without remaining of Ni atoms. This indicates the Ni atoms diffuse through the oxygen vacancies of ITO structure. Rapid thermal process (RTP) applied to generate an initial stage of a formation of Ni nanoparticles with variation in time periods to demonstrate the existence of an optimum condition to initiate ITO NW growth. Modulation in ITO sputtering condition was applied to verify the ITO NW growth or the ITO film growth. The Ni-assisted grown ITO layer has an improved electrical conductivity while maintaining a similar transmittance value to that of a single ITO layer. Electrically conductive and optically transparent nanowire-coated surface morphology would provide a great opportunity for various photoelectric devices.

• Korean Journal of Materials Research
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• v.16 no.9
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• pp.564-570
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• 2006

Silicides have been required to be below 40 nm-thick and to have low contact resistance without agglomeration at high silicidation temperature. We fabricated composite silicide layers on the wafers from Ni(20 nm)/Co(20 nm)/poly-Si(70 nm) structure by rapid thermal annealing of $700{\sim}1100^{\circ}C$ for 40 seconds. The sheet resistance, surface composition, cross-sectional microstructure, and surface roughness were investigated by a four point probe, a X-ray diffractometer, an Auger electron spectroscopy, a field emission scanning electron microscope, and a scanning probe microscope, respectively. The sheet resistance increased abruptly while thickness decreased as silicidation temperature increased. We propose that the fast metal diffusion along the silicon grain boundary lead to the poly silicon mixing and inversion. Our results imply that we may consider the serious thermal instability in designing and process for the sub-0.1 um CMOS devices.