• Transactions on Electrical and Electronic Materials
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• 제3권1호
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• pp.42-45
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• 2002

Properties of lead zirconate titanate ferroelectric thin films prepared by rapid thermal annealing/direct insertion thermal annealing were investigated. The remnant polarization (Pr), saturation polarization (Ps), and coercive force (Ec) of typical samples annealed by rapid thermal annealing (RTA) are about 13.7 $\mu$ C/cm$^2$, 27.1 $\mu$C/cm$^2$, and 55.6 kV/cm, respectively. The dielectric constant of the sample is about 786, the dielectric loss tangent is about 2.4% at 1 kHz. Furthermore, ferroelectric, conduction, and piezoelectric properties of the thin films annealed by RTA process and the direct insertion thermal annealing (DITA) process were compared. The influence of temperature in the dry process on the above properties was also investigated.

• 대한공업교육학회지
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• 제33권1호
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• pp.249-264
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• 2008

본 연구에서는 저 에너지 이온 주입과 이중 열처리를 통하여 박막 $p^+-n$ 접합을 형성하였고, 보론 확산 모델을 가지고 새로운 시뮬레이터를 설계하여 이온 주입과 열처리 후의 보론 분포를 재현하였다. $BF_2$ 이온을 가지고 실리콘 기판에 저 에너지 이온 주입을 하였고, 이후 RTA(Rapid Thermal Annealing)와 FA(Furnace Annealing)를 통하여 열처리 과정을 수행하였다. 시뮬레이션을 위한 확산 모델은 점결함의 생성과 재결합, BI 쌍의 생성, 보론의 활성화와 침전 현상 등을 고려하였다. FA+RTA 열처리가 RTA+FA 보다 면저항 측면의 접합 특성에서 우수한 결과를 나타내었고, 시뮬레이터에서도 동일한 결과를 나타내었다. 따라서 본 연구를 통하여 박막접합을 형성할 때 열적 효율성을 고려하면 제안된 확산 시뮬레이터와 FA+RTA 공정 방법의 유용성을 기대할 수 있다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제5권2호
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• pp.83-88
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• 2005

The interface-states between the top silicon layer and buried oxide layer of nano-SOI substrate were developed. Also, the effects of thermal treatment processes on the interface-state distributions were investigated for the first time by using pseudo-MOSFETs. We found that the interface-state distributions were strongly influenced by the thermal treatment processes. The interface-states were generated by the rapid thermal annealing (RTA) process. Increasing the RTA temperature over $800^{\circ}C$, the interface-state density considerably increased. Especially, a peak of interface-states distribution that contributes a hump phenomenon of subthreshold curve in the inversion mode operation of pseudo-MOSFETs was observed at the conduction band side of the energy gap, hut it was not observed in the accumulation mode operation. On the other hand, the increased interface-state density by the RTA process was effectively reduced by the relatively low temperature annealing process in a conventional thermal annealing (CTA) process.

• 한국표면공학회지
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• 제35권6호
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• pp.377-382
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• 2002

We investigated the appropriate wet cleaning process for Co-Ti-Si compounds formed on top of cobalt disilicide made from Co/Ti deposition and two rapid thermal annealing (RTA). We employed three wet cleaning processes, WP1 ($H_2$SO$_4$ etchant), WP2 ($NH_4$OH etchant), and WP3 which execute sequentially WP1 and WP2 after the first RTA. All samples were cleaned with BOE etchant after the second RTA. We characterized the sheet resistance with process steps by a four-point probe, the microstructure evolution by a cross detail sectional transmission electron microscope, a Auger depth profiler, and a X-ray diffractometer (XRD). We confirmed WP3 wet cleaning process were the most suitable to remove CoTiSi layer selectively.

• 한국산학기술학회논문지
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• 제22권2호
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• pp.26-32
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• 2021

카본 전극 페로브스카이트 태양전지의 광활성층을 형성하는데 열판, 오븐, 쾌속열처리로 방법을 달리하며 이때 광전기적 특성과 미세구조 변화를 확인하였다. Glass/FTO/compact TiO2/meso TiO2/meso ZrO2/perovskite/carbon electrode 구조의 페로브스카이트 태양전지 소자를 열판 공정, 오븐 공정, RTA(rapid thermal annealing) 공정을 이용하여 준비하였다. 이때 광전기적 특성과 미세구조를 solar simulator와 광학현미경, 장발산주사전자현미경을 이용하여 각 소자의 특성을 분석하였다. 광전기적 특성 분석 결과, RTA 공정을 이용하여 제작한 소자에서 가장 우수한 광전기적 특성을 확인할 수 있었다. 미세구조 분석 결과 열판 공정과 오븐 공정으로 제작한 시편은 카본 전극 상부에 과잉 페로브스카이트 상이 형성되고, RTA 공정으로 제작한 시편에서는 시편 상부에 과잉 페로브스카이트 상 없이, 균일한 페로브스카이트가 형성된 것을 확인할 수 있었다. 또한 단면 미세구조에서는 RTA 공정으로 제작한 소자가 다공성 카본 전극 층에 고밀도의 페로브스카이트 층을 형성하여 우수한 광전기적 특성을 나타내었다. 따라서 대면적 소자 제작의 공정시간을 고려한 새로운 열처리방안으로 RTA 방법의 채용 가능성을 확인하였다.

• 전기전자학회논문지
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• 제2권1호
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• pp.101-107
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• 1998

인(Phosphorus)을 1MeV로 이온 주입한 후 RTA를 실시하여 미세결함의 특성을 조사하고, 면저항, SRP, SIMS, XTEM 분석과 CMOS 구조에서 래치업 특성을 모의 실험하였다. 도즈량이 증가할수록 면저항은 낮아지고, Rp값은 도즈량이 $1{\times}10^{13}/cm^2,\;5{\times}10^{13}/cm^2,\;1{\times}10^{14}/cm^2$일때 각각 $1.15{\mu}m,\;1.15{\mu},\;1.10{\mu}m$로 나타났다. SIMS 측정결과는 열처리 시간이 길수록 농도의 최대치가 표면으로부터 깊어지고, 농도 또한 낮아짐을 확인하였다. XTEM 분석 결과는 열처리 전에는 결함측정이 불가능했으나, 측정되지 많은 미세결함이 열처리 후 이차결함으로 성장한 것으로 조사되었다. 모의 실험은 buried layer와 connecting layer 구조를 사용하였으며, buried layer보다 connecting layer가 래치업 특성이 우수함을 확인하였다. Connecting layer의 도즈량이 $1{\times}10^{14}/cm^2$이고 이온주입 에너지가 500KeV일 때 trigger current는 $0.6mA/{\mu}m$이상이었고, trigger voltage는 약 6V로 나타났다. Connecting layer의 이온주입 에너지가 낮을수록 래치업 저감효과가 더욱 우수함을 알 수 있었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권4호
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• pp.266-272
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• 2009

In the present work three dimensional process and device simulations were employed to study the performance variations with RTA. It is observed that with the increase in RTA temperature, the arsenic dopants from the source /drain region diffuse laterally under the spacer region and simultaneously acceptors (Boron) are redistributed from the central axis region of the fin towards the Si/SiO2 interface. As a consequence both drive current and peak cut-off frequency of an n-FinFET are observed to improve with RTA temperatures. Volume inversion and hence the flow of carries through the central axis region of the fin due to reduced scattering was found behind the performance improvements with increasing RTA temperature.

• 한국재료학회지
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• 제12권5호
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• pp.382-386
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• 2002

We studied growth and characterization of $SrBi_2Ta_2O_9$ (SBT) thin films fabricated by low temperature process under vacuum and/or oxygen ambient. A metal organic decomposition (MOD) method based on a spin-on technique and annealing process using a rapid thermal annealing (RTA) method was used to prepare the SBT films. The crystallinity of a ferroelectric phase of SBT thin films is related to the oxygen partial pressure during RTA process. Under an oxygen partial pressure higher than 30 Torr, the crystallization temperature inducing the ferroelectric SBT phase can be lowered to $650^{\circ}C$. Those films annealed at $650^{\circ}C$ in vacuum and oxygen ambient showed good ferroelectric properties, that is, the memory window of 0.5~0.9 V at applied voltage of 3~7 V and the leakage current density of 1.80{\times}10^{-8}$ A/$\textrm{cm}^2$ at an applied voltage of 5V. In comparison with the SBT thin films prepared at 80$0^{\circ}C$ in $O_2$ ambient by furnace annealing process, the SBT thin films prepared at $650^{\circ}C$ in vacuum and oxygen ambient using the RTA process showed a good crystallization and electrical properties which would be able to apply to the virtul device fabrication precess.

• 한국전기전자재료학회논문지
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• 제13권4호
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• pp.312-317
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• 2000

Ferroelectric S $r_{0.9}$/B $i_{2.1}$/T $a_{2}$/ $O_{9}$ solutions were synthesized using sol-gel process in which strontinum ethoxide bismuth ethoxide trantalum ethoxide were used a s startring materials. SBT thin films were coated on Pt/Ti/ $SiO_2$/Si substrates by spin-coating. rapid thermal annealing (RTA) was used to promote crystallization. Thin films were annealed at $700^{\circ}C$ for 1 hr in an oxygen atmosphere. This temperature is about 10$0^{\circ}C$ lower than the usual annealing temperature for SBT thin films. Pt top-electrode was deposited by sputtering and thin films were post-annealed at $700^{\circ}C$ for 30 min. to enhance electrical properties. As the RTA temperature increased the higher 2 $P_{r}$ values were obtained. At RTA temperature being 78$0^{\circ}C$ remanent polarization of S $r_{0.9}$/B $i_{2.1}$/T $a_{2}$/ $O_{9}$ thin film was 7.73 $\mu$C/cm $_2$ and the leakage current density was 1.14$\times$10$^{-7}$ A/c $m^2$ at 3 V. As RTA temperature increased the breakdown voltage was decreased. It is considered that the low-field breadown is caused by the rough surface of SBT films and forming bismuth metal in SBT thin films.films.lms.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2007년도 추계학술발표대회 및
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• pp.130.1-130.1
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• 2007