• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.4
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• pp.300-304
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• 2008

A novel characterization method was investigated to estimate the trap generation during the program /erase cycles in nand flash memory cell. Utilizing Fowler-Nordheim tunneling current, floating gate potential and oxide electric field, we established a quantitative model which allows the knowledge of threshold voltage (Vth) as a function of either program or erase operation time. Based on our model, the derived results proved that interface trap density (Nit) term is only included in the program operation equation, while both Nit and oxide trap density (Not) term are included in the erase operation equation. The effectiveness of our model was tested using 50 nm nand flash memory cell with floating gate type. Nit and Not were extracted through the analysis of Program/Erase speed with respect to the endurance cycle. Trap generation and cycle numbers showed the power dependency. Finally, with the measurement of the experiment concerning the variation of cell Vth with respect to program/erase cycles, we obtained the novel quantitative model which shows similar results of relationship between experimental values and extracted ones.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.54-57
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• 2002

In this study, a new programming method, to minimize the generation of Si-SiO$_2$ interface traps of scaled SONOS flash memory as a function of number of program/erase cycles has been proposed. In the proposed programming method, power supply voltage is applied to the gate, forward biased program voltage is applied to the source and the drain, while the substrate is left open, so that the program is achieved by Modified Fowler-Nordheim (MFN) tunneling of electron through the tunnel oxide over source and drain region. For the channel erase, erase voltage is applied to the gate, power supply voltage is applied to the substrate, and the source and drain are open. A single power supply operation of 3 V and a high endurance of 1${\times}$10$\^$6/ prograss/erase cycles can be realized by the proposed programming method. The asymmetric mode in which the program voltage is higher than the erase voltage, is more efficient than symmetric mode in order to minimize the degradation characteristics of scaled SONOS devices because electrical stress applied to the Si-SiO$_2$ interface is reduced by short programming time.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.1
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• pp.5-10
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• 2003

In this study, a new programming method to minimize the generation of Si-SiO$_2$interface traps of SONOS nonvolatile memory device as a function of number of porgram/erase cycles was proposed. In the proposed programming method, power supply voltage is applied to the gate. forward biased program voltage is applied to the source and the drain, while the substrate is left open, so that the program is achieved by Modified Fowler-Nordheim(MFN) tunneling of electron through the tunnel oxide over source and drain region. For the channel erase, erase voltage is applied to the gate, power supply voltage is applied to the substrate, and the source and dram are left open. Also, the asymmetric mode in which the program voltage is higher than the erase voltage, is more efficient than symmetric mode in order to minimize the degradation characteristics or SONOS devices because electrical stress applied to the Si-SiO$_2$interface is reduced due to short program time.

• Journal of IKEEE
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• v.24 no.1
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• pp.161-169
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• 2020

In order to reduce the manufacturing cost of MCU chips used in applications such as wireless chargers and USB-C, compared to DP-EEPROM (Double Poly EEPROM), which requires 3 to 5 additional process masks, it is even more necessary MTP(Multi-Time Programmable), which is less than one additional mask and have smaller unit cell size. In addition, in order to improve endurance characteristics and data retention characteristics of the MTP memory cell due to E/P(Erase / Program) cycling, the distribution of the V_TP(Program Threshold Voltage) and the V_TE(Erase Threshold Voltage) needs to be narrow. In this paper, we proposed a current-type BL S/A(Bit-Line Sense Amplifier) circuit, WM(Write Mask) circuit, BLD(BL Driver) circuit and a algorithm, which can reduce the distribution of program and V_T and erase V_T, through compare the target current by performing the erase and program pulse of the short pulse several times, and if the current specification is satisfied, the program or erase operation is no longer performed. It was confirmed that the 256Kb MTP memory fabricated in the Magnachip semiconductor 0.13㎛ process operates well on the wafer in accordance with the operation mode.

• KIPS Transactions on Computer and Communication Systems
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• v.5 no.1
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• pp.1-6
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• 2016

This paper focuses on algorithm innovation of NAND Flash Memory for enhancing cell lifetime. During flash memory read/write/erase, the voltage of a specific cell should be a valid voltage level. If not, we cannot read the data correctly. This type of interference/disturbance tends to be serious when program and erase operation will go on. This is because FN tunneling results in tunnel oxide damage due to increased trap site on repetitive high biased state. In order to resolve this problem, we make the cell degradation by reducing the amount of stress in terms of erase cell, resulting in minimizing the cell disturbance on erase verify.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.40-43
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• 2000

The electrons and holes trapped in the tunneling oxide and interface-states generated in the Si/SiO$_2$ interface during program/erase (P/E) operations are known to cause reliability problems which can deteriorate the cell performance and cause the V$_{th}$ window close. This deterioration is caused by the accumulation of electrons and holes trapped in the oxide near the drain and source side after each P/E cycle. we propose three new erase schemes to improve the cell's endurance characteristics: (1)adding a Reverse soft program cycle after the source erase operation, (2)adding a detrapping cycle after the source erase operation, (3)adding a convergence cycle after the source erase operation. (3) is the most effective performance among the three erase schemes have been implemented and shown to significantly reduce the V$_{th}$ window close problem. And we are able to design the reliable periperal circuit of flash memory by using the (3).(3).

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.2
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• pp.176-183
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• 2017

There is a problem of long erase and program times in testing large-density memories. Also, there is a need of testing the VT voltages of EEPROM cells at each step during the reliability test. In this paper, a cell verification module is designed for a 512kb EEPROM and a CG (control gate) driver is proposed for measuring the VT voltages of a split gate EEPROM having negative erase VT voltages. In the proposed cell verification module, asymmetric isolated HV (high-voltage) NMOS devices are used to apply negative voltages of -3V to 0V in measuring erase VT voltages. Since erasing and programming can be done in units of even pages, odd pages, or a chip in the test time reduction mode, test time can be reduced to 2ms in testing the chip from 4ms in testing the even and the odd pages.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.6
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• pp.558-569
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• 2017

In this paper, a 256Kb EEPROM IP aimed at battery applications using a single supply of 1.5V which is embedded into an MCU is designed. In the conventional cross-coupled VPP (boosted voltage) charge pump using a body-potential biasing circuit, cross-coupled PMOS devices of 5V in it can be broken by the junction or gate oxide breakdown due to a high voltage of 8.53V applied to them in exiting the program or erase mode. Since each pumping node is precharged to the input voltage of the pumping stage at the same time that the output node is precharged to VDD in the cross-coupled charge pump, a high voltage of above 5.5V is prevented from being applied to them and thus the breakdown does not occur. Also, all erase, even program, odd program, and all program modes are supported to reduce the times of erasing and programming 256 kilo bits of cells. Furthermore, disturbance test time is also reduced since disturbance is applied to all the 256 kilo bits of EEPROM cells at once in the cell disturb test modes to reduce the cell disturbance testing time. Lastly, a CG driver with a short disable time to meet the cycle time of 40ns in the erase-verify-read mode is newly proposed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.40-45
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• 2008

We developed small molecular organic nonvolatile $4F^2$ memory cells using metal layer evaporation followed by $O_2$ plasma oxidation. Our memory cells sandwich an upper ${\alpha}$-NPD layer, Al nanocrystals surrounded by $Al_2O_3$, and a bottom ${\alpha}$-NPD layer between top and bottom electrodes. Their nonvolatile memory characteristics are excellent: the $V_{th},\;V_p$ (program), $V_e$ (erase), memory margin ($I_{on}/I_{off}$), data retention time, and erase and program endurance were 2.6 V, 5.3 V, 8.5 V, ${\approx}1.5{\times}10^2,\;1{\times}10^5s$, and $1{\times}10^3$ cycles, respectively. They also demonstrated symmetrical current versus voltage characteristics and a reversible erase and program process, indicating potential for terabit-level nonvolatile memory.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.219-225
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• 2013

Program and erase characteristics of the elliptic gate all around (e-GAA) SONOS cell have been studied as the variation of eccentricity of the channel. An analytic program and erase model for the elliptic GAA SONOS cell is proposed and evaluated. The model shows that the ISPP (incremental-step-pulse programming) property is changed non-linearly as the eccentricity of the e-GAA SONOS cell is increased. It is differently from the well known linear relationship for that of 2D SONOS and even 3D circular SONOS cell with program bias. We can find that the simulation results of ISPP characteristics are in accord with the experimental data.