Journal of the Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회논문지)

The Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회)
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Trap Generation Analysis by Program/Erase Speed Measurements in 50 nm Nand Flash Memory

50nm 급 낸드플래시 메모리에서의 Program/Erase 스피드 측정을 통한 트랩 생성 분석

  • 김병택 (삼성전자 반도체총괄 메모리사업부 Flash PA팀) ;
  • 김용석 (삼성전자 반도체총괄 메모리사업부 Flash PA팀) ;
  • 허성회 (삼성전자 반도체총괄 메모리사업부 Flash PA팀) ;
  • 유장민 (삼성전자 반도체총괄 메모리사업부 Flash PA팀) ;
  • 노용한 (성균관대학교 정보통신공학부)
  • Published : 2008.04.01
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Abstract

A novel characterization method was investigated to estimate the trap generation during the program /erase cycles in nand flash memory cell. Utilizing Fowler-Nordheim tunneling current, floating gate potential and oxide electric field, we established a quantitative model which allows the knowledge of threshold voltage (Vth) as a function of either program or erase operation time. Based on our model, the derived results proved that interface trap density (Nit) term is only included in the program operation equation, while both Nit and oxide trap density (Not) term are included in the erase operation equation. The effectiveness of our model was tested using 50 nm nand flash memory cell with floating gate type. Nit and Not were extracted through the analysis of Program/Erase speed with respect to the endurance cycle. Trap generation and cycle numbers showed the power dependency. Finally, with the measurement of the experiment concerning the variation of cell Vth with respect to program/erase cycles, we obtained the novel quantitative model which shows similar results of relationship between experimental values and extracted ones.

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References

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