• IEIE Transactions on Smart Processing and Computing
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• v.5 no.5
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• pp.349-357
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• 2016

The era of the Internet of Things (IoT) is upon us. In this era, minimizing power consumption becomes a primary concern for system-on-chip designers. While traditional power minimization and dynamic power management (DPM) techniques have been heavily explored to improve the power efficiency of devices inside very large-scale integration (VLSI) platforms, there is one critical factor that is often overlooked, which is the power conversion efficiency of a power delivery network (PDN). This paper is a tutorial that focuses on the power conversion efficiency of the PDN, and introduces novel methods to improve it. Circuit-, architecture-, and system-level approaches are presented to optimize PDN designs, while case studies for three different VSLI platforms validate the efficacy of the introduced approaches.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.69-74
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• 2013

In this paper, the impact of integrating large number of I/O (Input-Output) and Core power Delivery Network (PDN) on a 6 layers Flip-Chip Ball Grid Array (FCBGA) package is investigated. The impact of core induced supply noise on high-speed I/O interfaces, and high-speed I/O interface's supply noise coupling to adjacent high-speed I/O interfaces' jitter impact are studied. Concurrent stress validation software is used to induce SSO noise on each individual I/O interfaces; and at the same time; periodic noise is introduced from Core PDN into the I/O PDN domain. In order to have the maximum coupling impact, a prototype package is designed to merge the I/O and Core PDN as one while impact on jitter on each I/O interfaces are investigated. In order to understand the impact of the Core to I/O and I/O to I/O noise, the on-die noise measurements were measured and results were compared with the original PDN where each I/O and Core PDN are standalone and isolated are used as a benchmark.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.6
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• pp.633-643
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• 2013

GDS format files, as well as layout of the chip are noticeably needed so as to analyze the PDN (Power Delivery Network) inside of IC; however, commercial IC in the market has not supported design information which is layout of IC. Within this, in terms of IC having on-chip PDN, characteristic of inside PDN of the chip is a core parameter to predict generated noise from power/ground planes. Consequently, there is a need to scrutinize extraction method for unknown PDN of the chip in this paper. To extract PDN of the chip without IC circuit information, the de-embedding test vehicle is fabricated based on IEC62014-3. Further more, the extracted inside PDN of chip from de-embedding technique adopts the Co-simulation model which composes PCB, QFN (Quad-FlatNo-leads) Package, and Chip for the PDN, applied Co-simulation model well corresponds with impedance from measured S-parameters up to 4 GHz at common measured and simulated points.

• Journal of Satellite, Information and Communications
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• v.9 no.4
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• pp.42-46
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• 2014

In this paper, a coil typed electromagnetic band gap (EBG) structure to be inserted in the printed circuit board (PCB) inner layer in order to stabilize the PCB power line is proposed and implemented for global-navigation satellite service (GNSS) with the bandwidth from 1.55GHz to 1.81GHz. From the measurement result of the PCB board including EBG structure, the insertion loss(S21) was measured below about -50dB. From these results, it is expected that the stabilization of power delivery network (PDN) structure in the PCB circuit design should be improved and the preparation to EMI will be effective.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1555_1556
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• 2009

전자기기에서 외부 Console로 사용되는 Touch Pad의 입력오류를 줄이기 위해서는 안정된 전원의 공급이 필요하다, 전원에서 발생하는 노이즈는 PDN(Power Delivery Network)의 임피던스에 의해서 발생하며, 이들 노이즈를 줄이기 위해서는 decoupling capacitor의 적절한 수량과 위치를 선정하여, PDN의 임피던스를 최소화해야 한다. 본 논문에서는 임피던스의 최소화를 위해서 Full-wave 시뮬레이션을 이용해서 임피던스 특성을 분석하고, VNA(Vector Network Analyzer)를 이용하여 주파수에 대한 PDN 임피던스를 측정하고, Touch Pad 구동용 지그를 이용해서 Time Domain에서의 임피던스 저감에 따른 노이즈 특성을 분석 비교하였다.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.1
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• pp.27-32
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• 2015

In this paper, a mushroom typed electromagnetic band gap (EBG) structure to be inserted in the printed circuit board (PCB) inner layer in order to stabilize the PCB power line is proposed for global-navigation satellite service (GNSS). In designing the proposed EBG structure, the target stop-bandwidth was designed from 1.55GHz to 1.81GHz including GNSS and mobile communication-related frequency bandwidth. In this bandwidth, the insertion loss(S21) was observed below about -40dB. From the simulation results, it is expected that the stabilization of power delivery network (PDN) structure in the PCB circuit design should be improved and the effective correspondence to EMI will be helpful.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.2
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• pp.3-14
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• 2013

In this paper, key design issues and considerations for Signal Integrity(SI) and Power Integrity(PI) of a TSV-based 3D IC are introduced. For the signal integrity and power integrity of a TSV-based 3-D IC channel, analytical modeling and analysis results of a TSV-based 3-D channel and power delivery network (PDN) are presented. In addition, various design techniques and solutions which are to improve the electrical performance of a 3-D IC are investigated.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.7
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• pp.753-759
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• 2014

This paper introduces the reduction design technique of the resonance phenomenon of the inner PCB based on power integrity from the analysis about the inner power supply line generating RLC resonance. With the technique, the resonant frequency resulted from the structural characteristics of the PCB can be analyzed and allows to predict and the capacitor for resonance phenomenon reduction can be decided as a decoupling capacitor. From the simulation result, it was confirmed that the PCB's resonance phenomenon reduction design technique should have the reduction effect in the inner motherboard of the industrial controller. This research will be contributed to the improvement of the safety of a PDN (Power Delivery Network) structure in the layout design technique of the PCB.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1601_1602
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• 2009

본 논문은 SSN(Simultaneous Switching Noise) 이 유전체를 통해 다른 시스템에 유기되는 것을 막기 위한 방법인 EBG(Electromagnetic Band-Gap)에 관한 연구이다. 이에 대한 EBG 구조를 설계하기 위해 PDN(Power Delivery Network)에 주기적인 패턴을 삽입한다. 패키지에 EBG 구조를 적용하기 위해 인쇄 회로기판 범위에서 연구되었던 구조를 변형 및 개조하여 EBG 구조가 내포하고 있는 필터의 차단 주파수의 범위를 넓히며 차단 시작 주파수를 1GHz 아래로 낮추는 소형화 방법을 모색한다. 이 연구에서 실시할 EBG 구조에 대한 간단한 고찰과 인쇄 회로 기판에 적합한 AI-EBG(Alternating impedance Electromagnetic Band-Gap) 구조를 이용한 EBG 의 소형화에 대해 언급하고, 소형화를 위한 3-D EBG 의 설계구조에 대해 설명한다. 그리고 저주파에서 차단특성을 높이기 위한 방법으로 3-D EBG를 사용하고 AI-EBG와 비교하여 차단특성의 변화를 Full-wave 시뮬레이션과 측정으로서 비교한다.