[KSCI] Korea Science Citation Index Service

http://dx.doi.org/10.6117/kmeps.2013.20.4.069

Analyzing the Impact of Supply Noise on Jitter in GBPS Serial Links on a Merged I/O-Core Power Delivery Network

Tan, Fern-Nee (Malaysia Design Center, Intel Microelectronics)
Lee, Sheng Chyan (Department of Electronic and Green Technology, Tunku Abdul Rahman University)

Publication Information

Journal of the Microelectronics and Packaging Society / v.20, no.4, 2013 , pp. 69-74 More about this Journal

Abstract

In this paper, the impact of integrating large number of I/O (Input-Output) and Core power Delivery Network (PDN) on a 6 layers Flip-Chip Ball Grid Array (FCBGA) package is investigated. The impact of core induced supply noise on high-speed I/O interfaces, and high-speed I/O interface's supply noise coupling to adjacent high-speed I/O interfaces' jitter impact are studied. Concurrent stress validation software is used to induce SSO noise on each individual I/O interfaces; and at the same time; periodic noise is introduced from Core PDN into the I/O PDN domain. In order to have the maximum coupling impact, a prototype package is designed to merge the I/O and Core PDN as one while impact on jitter on each I/O interfaces are investigated. In order to understand the impact of the Core to I/O and I/O to I/O noise, the on-die noise measurements were measured and results were compared with the original PDN where each I/O and Core PDN are standalone and isolated are used as a benchmark.

Keywords

Simultaneous switching output (SSO); PCI-Express (PCIe); Serial-ATA (SATA); Universal Serial Bus (USB); Power delivery network (PDN); Flip-Chip Ball grid array (FCBGA);

Citations & Related Records

Reference

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