The Proceeding of the Korean Institute of Electromagnetic Engineering and Science (한국전자파학회지:전자파기술)

The Korean Institute of Electromagnetic Engineering and Science (한국전자파학회)
권호 표지

Overview of 3-D IC Design Technologies for Signal Integrity (SI) and Power Integrity (PI) of a TSV-Based 3D IC

  • Published : 2013.03.31
Download PDF
⟨ Previous Next ⟩

Abstract

In this paper, key design issues and considerations for Signal Integrity(SI) and Power Integrity(PI) of a TSV-based 3D IC are introduced. For the signal integrity and power integrity of a TSV-based 3-D IC channel, analytical modeling and analysis results of a TSV-based 3-D channel and power delivery network (PDN) are presented. In addition, various design techniques and solutions which are to improve the electrical performance of a 3-D IC are investigated.

Keywords

References

  1. C. Ryu, J. Lee, H. Lee, K. Lee, T. Oh, and J. Kim, "High frequency electrical model of through wafer via for 3-D stacked chip packaging," in IEEE Proc. Electron. Syst. Integration Technol. Conf., Sep. pp. 215-220, 2006.
  2. K. J. Han, Madhavan Swaminathan, and T. Bandyopadhyay, "Electromagnetic modeling of Through- Silicon Via (TSV) interconnections using cylindrical modal basis functions", IEEE Transactions on Advanced Packaging, vol. 33, no. 4, pp. 804-817, Nov. 2010. https://doi.org/10.1109/TADVP.2010.2050769
  3. I. Savidis, E. G. Friedman, "Closed-form expressions of 3-D via resistance, inductance, and capacitance", IEEE Transactions on Electron Devices, vol. 56, no. 9, pp. 1873-1881, Sep. 2009. https://doi.org/10.1109/TED.2009.2026200
  4. J. Kim, J. S. Pak, J. Cho, E. Song, J. Cho, H. Kim, T. Song, J. Lee, H. Lee, K. Park, S. Yang, M. Suh, K. Byun, and J. Kim, "High-frequency scalable electrical model and analysis of a Through Silicon Via (TSV)", IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 1, no. 2, pp. 181-195, Feb. 2011. https://doi.org/10.1109/TCPMT.2010.2101890
  5. G. Katti, M. Stucchi, K. De Meyer, and W. Dehaene, "Electrical modeling and characterization of through silicon via for three-dimensional ICs", IEEE Transactions on Electron Devices, vol. 57, no. 1, pp. 256-262, Jan. 2010. https://doi.org/10.1109/TED.2009.2034508
  6. J. Cho, M. Kim, J. Kim, J. Pak, H. Lee, J. Lee, K. Park, and J. Kim, "Through-silicon via (TSV) depletion effect", IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), pp. 101-104, 23-26 Oct. 2011.
  7. J. Cho, E. Song, K. Yoon, J. Pak, J. Kim, W. Lee, T. Song, K. Kim, J. Lee, H. Lee, K. Park, S. Yang, M. Suh, K. Byun, and J. Kim, "Modeling and analysis of Through-Silicon-Via (TSV) moise coupling and suppression using a guard ring", IEEE Transactions on Components, Packaging, and Manufacturing Technology, vol. 1, no. 2, pp. 220-233, Feb. 2011. https://doi.org/10.1109/TCPMT.2010.2101892
  8. T. Song, C. Liu, D. Kim, S. Lim, J. Cho, J. Kim, J. Pak, S. Ahn, J. Kim, and K. Yoon, "Analysis of TSV-to-TSV coupling with high-impedance termination in 3D ICs", Quality Electronic Design (ISQED), 2011 12th International Symposium on, pp. 1,7, 14-16, Mar. 2011.
  9. J. Cho, "Noise Coupling Analysis and Reduction in 3D-IC considering Through-Silicon Via (TSV) non linearity", Ph.D. Dissertation, KAIST, Daejeon, 2013.
  10. M. Lee, J. Cho, J. Kim, J. Pak, H. Lee, J. Lee, K. Park, and J. Kim, "Temperature-dependent throughsilicon via (TSV) model and noise coupling", IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), pp. 247- 250, Oct. 2011.
  11. G. Katti, M. Stucchi, D. Velenis, B. Soree, K. De Meyer, and W. Dehaene, "Temperature-dependent modeling and characterization of through-silicon via capacitance", IEEE Electron Device Letters, vol. 32, no. 4, pp. 563-565, Apr. 2011. https://doi.org/10.1109/LED.2011.2109052
  12. H. Kim, J. Cho, J. Kim, K. Kim, S. Choi, J. Kim, and J. Pak, "A compact on-interposer passive equalizer for chip-to-chip high-speed data transmission", IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), pp. 95-98, Oct. 2012.
  13. J. Pak, J. Kim, J. Cho, K. Kim, T. Song, S. Ahn, J. Lee, H. Lee, K. Park, and J. Kim, "PDN impedance modeling and analysis of 3D TSV IC by using proposed P/G TSV array model based on separated P/G TSV and Chip-PDN models", Components, Packaging and Manufacturing Technology, IEEE Transactions on, vol. 1, no. 2, pp. 208-219, Feb. 2011. https://doi.org/10.1109/TCPMT.2010.2101771
  14. J. Kim, W. Lee, Y. Shim, J. Shim, K. Kim, J. S. Pak, and J. Kim, "Chip-package hierarchical power distribution network modeling and analysis based on a segmentation method", Advanced Packaging, IEEE Transactions on, vol. 33, no. 3, pp. 647-659, Aug. 2010. https://doi.org/10.1109/TADVP.2010.2043673
  15. K. Kim, W. Lee, J. Kim, T. Song, J. Kim, J. Pak, H. Lee, Y. Kwon, K. Park, and J. Kim, "Analysis of power distribution network in TSV-based 3DIC", IEEE 19th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), pp. 177-180, Oct. 2010.
  16. E. Song, J. Pak, and J. Kim, "TSV-based decoupling capacitor schemes in 3D-IC", IEEE 62nd Electronic Components and Technology Conference (ECTC), pp. 1340-1344, May 29 2012-Jun. 1 2012.