• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.5
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• pp.35-41
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• 2008

This paper presents the design method of current-mode signal processing for high speed and low power digital audio signal processing. The digital audio processor requires a digital signal processing such as fast Fourier transform (FFT), which has a problem of large power consumption according to the settled point number and high speed operation. Therefore, a current-mode signal processing with a switched Current (SI) circuit was employed to the digital audio signal processing because a limited battery life should be considered for a low power operation. However, current memory that construct a SI circuit has a problem called clock-feedthrough. In this paper, we examine the connection of dummy MOS that is the common solution of clock-feedthrough and are willing to calculate the relation of width between dummy MOS for a proposal of the design methodology for improvement of current memory. As a result of simulation, in case of that the width of memory MOS is 20um, ratio of input current and bias current is 0.3, the relation of width between switch MOS and dummy MOS is $W_{M4}=1.95W_{M3}+1.2$ for the width of switch MOS is 2~5um, it is $W_{M4}=0.92W_{M3}+6.3$ for the width of switch MOS is 5~10um. Then the defined relation of MOS transistors can be a useful design guidance for a high speed low power digital audio processor.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.6
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• pp.584-597
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• 2011

In this paper, low-loss and high-power RF SP6T switch chips are designed, fabricated and measured for GSM/EGSM/DCS/PCS applications using WIN Semiconductors 0.5 ${\mu}m$ pHEMT process. We utilized a combined configuration of series and series-shunt structures for optimized switch performance, and a common transistor structure on a receiver path for reducing chip area. The gate width and the number of stacked transistors are determined using ON/OFF input power level of the transceiver system. To improve the switch performance, feed-forward capacitors, shunt capacitors and parasitic FET inductance elimination due to resonance are actively used. The fabricated chip size is $1.2{\times}1.5\;mm^2$. S-parameter measurement shows an insertion loss of 0.5~1.2 dB and isolation of 28~36 dB. The fabricated SP6T switch chips can handle 4 W input power and suppress second and third harmonics by more than 75 dBc.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.17-26
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• 2016

This work proposes a 12b 60MS/s 0.18um CMOS Flash-SAR ADC for various systems such as wireless communications and portable video processing systems. The proposed Flash-SAR ADC alleviates the weakness of a conventional SAR ADC that the operation speed proportionally increases with a resolution by deciding upper 4bits first with a high-speed flash ADC before deciding lower 9bits with a low-power SAR ADC. The proposed ADC removes a sampling-time mismatch by using the C-R DAC in the SAR ADC as the combined sampling network instead of a T/H circuit which restricts a high speed operation. An interpolation technique implemented in the flash ADC halves the required number of pre-amplifiers, while a switched-bias power reduction scheme minimizes the power consumption of the flash ADC during the SAR operation. The TSPC based D-flip flop in the SAR logic for high-speed operation reduces the propagation delay by 55% and the required number of transistors by half compared to the conventional static D-flip flop. The prototype ADC in a 0.18um CMOS demonstrates a measured DNL and INL within 1.33LSB and 1.90LSB, with a maximum SNDR and SFDR of 58.27dB and 69.29dB at 60MS/s, respectively. The ADC occupies an active die area of $0.54mm^2$ and consumes 5.4mW at a 1.8V supply.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.214.1-214.1
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• 2015

Thin-film transistors (TFTs)의 채널층으로 널리 쓰이는 indium-gallium-zinc oxide (IGZO)는 높은 전자 이동도(약 10 cm2/Vs)를 나타내며 유기 발광 다이오드디스플레이(OLED)와 대면적 액정 디스플레이(LCD)에 필수적으로 사용되고 있다. 하지만, 이러한 재료는 우수한 TFT의 채널층의 특성을 가지는 반면, ZnO 기반 재료이기 때문에 소자 구동에서의 안정성은 가장 큰 문제로 남아있다. 따라서 최근, IGZO layer의 특성을 향상시키기 위한 연구가 다양한 방법으로 시도되고 있다. IGZO의 조성비를 조절하여 전기적 특성을 최적화거나 IGZO layer의 조성 중 Ga을 다른 금속 메탈로 대체하는 연구도 이루어지고 있다. 그러나 IGZO에 미량의 도펀트를 첨가하여 박막 특성 변화를 관찰한 연구는 거의 진행되지 않고 있다. 산화물 TFTs의 전기적 특성과 안정성은 산소 함량에 영향을 많이 받는 것으로 알려져 있으며, 더욱이 TFT 채널층으로 쓰이는 IGZO 박막의 고유한 산소 공공은 디바이스 작동 중 열적으로 활성화 되어 이온화 상태가 될 때 소자의 안정성을 저하시키는 것이 문제점으로 지적되고 있다. 그러므로 본 연구에서는 낮은 전기 음성도(1.22)와 표준전극전위(-2.372 V)를 가지며 산소와의 높은 본드 엔탈피 값(719.6 kJ/mol)을 가짐으로써 산소 공공생성을 억제할 것으로 기대되는 yttrium을 IGZO의 도펀트로 도입하였다. 따라서 본 연구에서는 Y-IGZO의 박막 특성 변화를 관찰하고자 한다. 본 연구에서는 magnetron co-sputtering법으로 IGZO 타깃(DC)과 Y2O3 타깃(RF)를 이용하여 기판 가열 없이 동시 방전을 이용해 non-alkali glass 기판 위에 증착 하였다. IGZO 타깃은 DC power 110 W으로 고정하였으며 Y2O3 타깃에는 RF Power를 50 W에서 110 W까지 증가시키면서 Y 도핑량을 조절하였다. Working pressure는 고 순도 Ar을 20 sccm 주입하여 0.7 Pa로 고정하였다. 모든 실험은 $50{\times}50mm$ 기판 위에 총 두께 $50nm{\pm}2$ 박막을 증착 하였으며, 그 함량에 따른 전기적 특성 및 광학적 특성을 살펴보았다. 또한, IGZO 박막 제조 시 박막의 안정화를 위해 열처리과정은 필수적이다. 하지만 본 연구에서는 열처리를 진행하지 않고 Y-IGZO의 안정성 개선 여부를 보기 위하여 20일 동안 상온에서 방치하여 그 전기적 특성변화를 관찰하였다. 나아가 Y-IGZO 채널 층을 갖는 TFT 소자를 제조하여 소자 구동 특성을 관찰 하였다. Y2O3 타깃에 가해지는 RF Power가 70 W 일 때 Y-IGZO박막은 IGZO박막과 비교하여 상대적으로 캐리어 밀도는 낮은 반면 이동도는 높은 최적 특성을 얻을 수 있었다. 상온방치 결과 Y-IGZO박막은 IGZO박막에 비해 전기적 특성 변화 폭이 적었으며 이것은 Y 도펀트에 의한 안정성 개선의 결과로 예상된다. 투과도는 Y 도핑에 의하여 약 1.6 % 정도 상승하였으며 밴드 갭 내에서 결함 준위로 작용하는 산소공공의 억제로 인한 결과로 판단된다.

• Journal of IKEEE
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• v.24 no.3
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• pp.859-866
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• 2020

This paper proposes a 2-ch DC-DC converter with a wide-input voltage range from 2.9V~5.6V for wearable AMOLED displays. For positive voltage V_POS, a boost converter is designed using an over-charged voltage permissible circuit (OPC) which generates a normal output voltage even if over-input voltage is applied, and a SPWM-PWM dual mode with 3-segmented power transistors to improve efficiency at light load. For negative voltage V_NEG, a 0.5x regulated inverting charge pump is designed to increase power efficiency. The proposed DC-DC converter was designed using a 0.18-㎛ BCDMOS process. Simulation results show that the proposed DC-DC converter generates V_POS voltages of 4.6 V and V_NEG voltage of -0.6V~-2.3V for input voltage of 2.9V to 5.6V. In addition, it has power efficiency of 49%~92%, output ripple voltage has less than 20 mV for load current range of 1 mA~70 mA.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.458-461
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• 2015

In this paper 2 types of voltage references and a current reference suitable for low-voltage, low-power circuits are proposed and designed with $0.35{\mu}m\;CMOS$ process. MOS transistors operating in weak inversion and bulk-driven technique are utilized to achieve low-voltage and low-power features. The first voltage reference consumes 1.43uA from a supply voltage of 1.2V while it has a reference voltage of 585mV and a TC(Temperature Coefficient) of $6ppm/^{\circ}C$. The second voltage reference consumes 48pW from a supply voltage of 0.3V while having a reference voltage of 172mV and a TC of $26ppm/^{\circ}C$. The current reference consumes 246nA from a supply voltage of 0.75V with a reference current of 32.6nA and a TC of $262ppm/^{\circ}C$. The performances of the designed references have been verified through simulations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.71-80
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• 2007

This paper presents a new push-push VCO technique that extracts a second harmonic output signal from a capacitive commonnode in a negativegm oscillator topology. The generation of the $2^{nd}$ harmonics is accounted for by the nonlinear current-voltage characteristic of the emitter-base junction diode causing; 1) significant voltage clipping and 2) different rising and falling time during the switching operation of core transistors. Comparative investigations show the technique is more power efficient in the high-frequency region that a conventional push-push technique using an emitter common node. Prototype 12GHz and 17GHz MMIC VCO were realized in GaInP/GaAs HBT technology. They have shown nominal output power of -4.3dBm and -5dBm, phase noise of -108 dBc/Hz and -110.4 dBc/Hz at 1MHz offset, respectively. The phase noise results are also equivalent to a VCO figure-of-merit of -175.8 dBc/Hz and -184.3 dBc/Hz, while dissipate 25.68mW(10.7mA/2.4V) and 13.14mW(4.38mA/3.0V), respectively.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.3
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• pp.152-162
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• 2003

In this paper, Binary to Quaternary Converter(BQC), Quaternary to Binary Converter(QBC) and Quaternary inverter circuit, which is the basic logic gate, have been proposed based on voltage mode. The BQC converts the two bit input binary signals to one digit quaternary output signal. The QBC converts the one digit quaternary input signal to two bit binary output signals. And two circuits consist of Down-literal circuit(DLC) and combinational logic block(CLC). In the implementation of quaternary inverter circuit, DLC is used for reference voltage generation and control signal, only switch part is implemented with conventional MOS transistors. The proposed circuits are simulated in 0.35 ${\mu}{\textrm}{m}$ N-well doubly-poly four-metal CMOS technology with a single +3V supply voltage. Simulation results of these circuit show 250MHz sampling rate, 0.6mW power consumption and maintain output voltage level in 0.1V.

• Bulletin of the Korean Chemical Society
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• v.32 no.spc8
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• pp.2899-2905
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• 2011

We have demonstrated that TPyPA can be used as an efficient multi-functional material for OLEDs; hole transporting material (HTL), blue and white-light emitter. The device based on TPyPA as the HTL exhibited an external quantum efficiency of 1.7% and a luminance efficiency of 4.2 cd/A; these values are 40% higher than the external quantum efficiency and luminance efficiency of the NPD-based reference device. The device based on TPyPA as a blue-light emitter exhibited an external quantum efficiency of 4.2% and a luminance efficiency of 5.3 $cdA^{-1}$ with CIE coordinates at (0.16, 0.14), the device based on TPyPA as a white-light emitter exhibited an external quantum efficiency of 3.2% and a luminance efficiency of 7.7 $cdA^{-1}$ with CIE coordinates at (0.33, 0.39). Also, TPyPA-based organic solar cell (OSC) exhibited a maximum power conversion efficiency of 0.35%. TPyPA-based organic thin-film transistors (OTFTs) exhibited highly efficient field-effect mobility (${\mu}_{FET}$) of $1.7{\times}10^{-4}cm^2V^{-1}s^{-1}$, a threshold voltage ($V_{th}$) of -15.9 V, and an on/off current ratio of $8.6{\times}10^3$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.10
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• pp.52-62
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• 2003

This paper discusses ternary logic gate, ternary D flip-flop, and ternary four-digit parallel input/output register. The ternary logic gates consist of n-channel pass transistors and neuron MOS(νMOS) threshold inverters on voltage mode. They are designed with a transmission function using threshold inverter that are in turn, designed using Down Literal Circuit(DLC) that has various threshold voltages. The νMOS pass transistor is very suitable gate to the multiple-valued logic(MVL) and has the input signal of the multi-level νMOS threshold inverter. The ternary D flip-flop uses the storage element of the ternary data. The ternary four-digit parallel input/output register consists of four ternary D flip-flops which can temporarily store four-digit ternary data. In this paper, these circuits use 3.3V low power supply voltage and 0.35m process parameter, and also represent HSPICE simulation result.