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Quaternary Multiplier Circuit
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[
Wei-Shang Chu;Wayne Current
] /
Proc. 24th ISMVL
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2 |
Evolutionary methods in the Design of Quaternary digital Circuits
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[
Claudio Maraga;Wenjun Wang
] /
Proc. 28th ISMVL
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3 |
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Jing Shen, Motoi Inaba, Koichi Tanno, Okihiko Ishizuka, 'Multi-Valued Logic Pass Gate network Using Neuron-MOS Transistors', Proc, 30th ISMVL, pp. 15-20, 2000
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Makoto Syuto, Jing Shen, Koichi Tanno and Okihiko Ishizuka, 'Multi-Input Variable-Threshold Circuits for Multi - Valued Logic Functions', Proc, 30th ISMVL, pp. 27-32, 2000
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17 |
K. W. Current, 'Design of a Quaternary Latch Circuit Using a Binary CMOS RS Latch', Proc. 30th ISMVL, pp. 377 - 381, 2000
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Kota Mitsuya, Noriaki Muranaka, Sigeru Imanishi, 'A Composition of Full Adder using Neuron MOSFETs by Ternary Signed Digit Number Representation', Proc, The first Korea-Japan joint symposium, August 1999
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Andreas Herrfeld and Siegbert Hentschke, 'Quaternary Dynamic differential Logic With Application to Fuzzy-Logic Circuits', Proc. 27th ISMVL, pp. 215-220, 1997
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21 |
Jing Shen, Koichi Tanno, Okihiko Ishizuka, 'Down Literal Circuit with Neuron-MOS Transistors and Its Applications', Proc. 29th ISMVL, pp. 180-184. 1999
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22 |
Claudio Moraga, Wenjun Wang, 'Evolutionary methods in the Design of Quaternary digital Circuits', Proc. 28th ISMVL, pp. 89-92, 1998
DOI
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23 |
Wei-Shang Chu and Wayne Current, 'Quaternary Multiplier Circuit', Proc. 24th ISMVL, pp. 15-16, 1994
DOI
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24 |
Makoto Syuto, Jing Shen, Koichi Tanno and Okihiko Ishizuka, 'Voltage-Mode Linear Summation Circuit with Neuron-MOS Transistors and Its Application to Multi-Valued Logic', Proc, The first Korea-Japan joint symposium, August 1999
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25 |
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26 |
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