• Journal of Educational Research in Mathematics
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• v.8 no.2
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• pp.527-540
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• 1998

In the teacher's guide of mathematics textbook for the 1st grade of the middle school, the clear and logical reason why the multiplication of negative number to negative number makes positive number, and $a^{-m}$ with a>0 and m>0, is defined by ${\frac{1}{a^m}}$ is not given. When we define the multiplication or the power by successive addition or successive multiplication of the same number, respectively, we encounter this ambiguity, in the case that the number of successive operations is negative, In this paper, we name this number, negative counting number, and we make the following more logical and intuitive definition, which is "negatively many successive operations is defined by positively many successive inverse operations." According to this new definition, we define the multiplication by the successive addition or the successive subtraction of the same number, when the multiplier is positive or negative respectively, and the power by the successive multiplication or the power is positive or negative, respectively. In addition, using this new definition and following the E.R.S Instruction strategy which revised and complemented the Bruner's E.I.S Instruction strategy, we develope new teaching model available in the 1st grade class of middle school where the concept of integers, three operations of integers are introduced.ntroduced.

• ETRI Journal
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• v.36 no.4
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• pp.643-653
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• 2014

To reduce interconnect delay and power consumption while improving chip performance, a three-dimensional integrated circuit (3D IC) has been developed with die-stacking and through-silicon via (TSV) techniques. The power supply problem is one of the essential challenges in 3D IC design because IR-drop caused by insufficient supply voltage in a 3D chip reduces the chip performance. In particular, power bumps and TSVs are placed to minimize IR-drop in a 3D power delivery network. In this paper, we propose a design methodology for 3D power delivery networks to minimize the number of power bumps and TSVs with optimum mesh structure and distribute voltage variation more uniformly by shifting the locations of power bumps and TSVs while satisfying IR-drop constraint. Simulation results show that our method can reduce the voltage variation by 29.7% on average while reducing the number of power bumps and TSVs by 76.2% and 15.4%, respectively.

• Bulletin of the Korean Mathematical Society
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• v.57 no.1
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• pp.245-250
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• 2020

Let γt(G) and τ(G) denote the total domination number and vertex cover number of graph G, respectively. In this paper, we study the total domination number of the central tree C(T) for a tree T. First, a relationship between the total domination number of C(T) and the vertex cover number of tree T is discussed. We characterize the central trees with equal total domination number and independence number. Applying the first result, we improve the upper bound on the total domination number of C(T) and solve one open problem posed by Kazemnejad et al..

• ETRI Journal
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• v.27 no.5
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• pp.504-510
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• 2005

This paper proposes a novel low-power video decoding scheme. In the encoded video bitstream, there is quite a large number of non-coded blocks. When the number of the non-coded blocks in a frame is known at the start of frame decoding, the workload of the video decoding can be estimated. Consequently, the supply voltage of very large-scale integration (VLSI) circuits can be lowered, and the power consumption can be reduced. In the proposed scheme, the encoder counts the number of non-coded blocks and stores this information in the frame header of the bitstream. Simulation results show that the proposed scheme reduces the power consumption to about 1/10 to 1/20.

• Journal of applied mathematics & informatics
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• v.28 no.1_2
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• pp.539-551
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• 2010

Low scalability and power efficiency of the shared bus in SoCs is a motivation to use on chip networks instead of traditional buses. In this paper we have modified the Orion power model to reach an analytical model to estimate the average message energy in K-Ary n-Cubes with focus on the number of virtual channels. Afterward by using the power model and also the performance model proposed in [11] the effect of number of virtual channels on Energy-Delay product have been analyzed. In addition a cycle accurate power and performance simulator have been implemented in VHDL to verify the results.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.4
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• pp.745-750
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• 2007

In this paper, we propose a new gate modification method using the input vector maximizes the number of gates in WLS within the optimum range of the minimum leakage power. We prove that MLV is not always the optimal solution, and that the leakage power and area can decrease when modifying the gates using the input vector for which the number of gates in WLS is maximized within the optimum range of the minimum leakage power for the circuits applying the IVC technique and gate modification method. Using the proposed method, the gate-level description circuit can be converted to the modified circuit which reduces the leakage power by chip designer, and the modified circuit can be applied without any modification in design flow.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1165-1168
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• 2003

In this paper, a CLB-based CPLD low-power technology mapping algorithm is proposed. To perform low power technology mapping for CPLD, a given Boolean network have to be represented to DAG. The proposed algorithm are consist of three step. In the first step, TD(Transition Density) calculation have to be performed. In the second step, the feasible clusters are generated by considering the following conditions: the number of output, the number of input and the number of OR-terms for CLB(Common Logic Block) within a CPLD. The common node cluster merging method, the node separation method, and the node duplication method are used to produce the feasible clusters. In the final step, low power technology mapping based on the CLBs is packing the feasible clusters into the several proper CLBs. Therefore the proposed algorithm is proved an efficient algorithm for a low power CPLD technology mapping.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.45 no.3
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• pp.432-437
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• 1996

This paper describes a diagnostic technique of power transformers by on-line detection of ultrasonic signals. A trend of partial discharge variation in a real transformer was estimated by counting the number of ultrasonic signals until insulation paper in the point-to-plane electrode is punctured. The number of electrical signals is closely related to the ultrasonic signals generated by partial discharge. The trend of the ultrasonic signal number could easily be distinguished by taking moving average. The insulation failure due to partial discharge in transformers can be predicted based on the trend analysis of ultrasonic signal number caused by partial discharge. (author). 14 refs., 10 figs.

• Journal of Digital Contents Society
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• v.14 no.1
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• pp.1-5
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• 2013

In this paper a study of efficient CPLD low power algorithm is proposed. Proposed algorithm applicate graph partition method using DAG. Circuit representation DAG. Each nodes set up cost. The feasible cluster create according to components of CPLD. Created feasible cluster generate power consumption consider the number of OR-term, the number of input and the number of output. Implement a circuit as select FC having the minimum power consumption. Compared with experiment [9], and power consumption was decreased. The proposed algorithm is efficient. this paper, we proposed FPGA algorithm for consider the power consumption.

• Journal of Power Electronics
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• v.13 no.5
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• pp.787-797
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• 2013

Despite the advantages offered by multilevel inverters, one of the main drawbacks that prevents their widespread use is their circuit complexity as the number of power switches employed is usually high. This paper presents a new multilevel inverter topology with a considerable reduction in the number of power switches used through the switch-sharing approach. The fact that the proposed inverter applies two bidirectional power switches for sharing among the three phases does not prevent it from producing seven levels in the line-to-line output voltage waveforms. A modified scheme of space vector modulation via the application of virtual voltage vectors is developed to generate the PWM signals of the power switches. The performance of the proposed inverter is investigated through MATLAB/SIMULINK simulations and is practically tested using a laboratory prototype with a DSP-based modulator. The results demonstrate the satisfactory performance of the inverter and verify the effectiveness of the modulation method.